Lines Matching +full:port +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2022 NVIDIA Corporation
18 #include <dt-bindings/gpio/tegra186-gpio.h>
19 #include <dt-bindings/gpio/tegra194-gpio.h>
20 #include <dt-bindings/gpio/tegra234-gpio.h>
21 #include <dt-bindings/gpio/tegra241-gpio.h>
79 unsigned int port; member
113 void __iomem *base; member
121 for (i = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_get_port()
122 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; in tegra186_gpio_get_port() local
124 if (*pin >= start && *pin < start + port->pins) { in tegra186_gpio_get_port()
125 *pin -= start; in tegra186_gpio_get_port()
126 return port; in tegra186_gpio_get_port()
129 start += port->pins; in tegra186_gpio_get_port()
138 const struct tegra_gpio_port *port; in tegra186_gpio_get_base() local
141 port = tegra186_gpio_get_port(gpio, &pin); in tegra186_gpio_get_base()
142 if (!port) in tegra186_gpio_get_base()
145 offset = port->bank * 0x1000 + port->port * 0x200; in tegra186_gpio_get_base()
147 return gpio->base + offset + pin * 0x20; in tegra186_gpio_get_base()
153 const struct tegra_gpio_port *port; in tegra186_gpio_get_secure_base() local
156 port = tegra186_gpio_get_port(gpio, &pin); in tegra186_gpio_get_secure_base()
157 if (!port) in tegra186_gpio_get_secure_base()
160 offset = port->bank * 0x1000 + port->port * TEGRA186_GPIO_SCR_PORT_SIZE; in tegra186_gpio_get_secure_base()
162 return gpio->secure + offset + pin * TEGRA186_GPIO_SCR_PIN_SIZE; in tegra186_gpio_get_secure_base()
172 if (gpio->soc->has_vm_support) { in tegra186_gpio_is_accessible()
206 void __iomem *base; in tegra186_gpio_get_direction() local
209 base = tegra186_gpio_get_base(gpio, offset); in tegra186_gpio_get_direction()
210 if (WARN_ON(base == NULL)) in tegra186_gpio_get_direction()
211 return -ENODEV; in tegra186_gpio_get_direction()
213 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_get_direction()
224 void __iomem *base; in tegra186_gpio_direction_input() local
227 base = tegra186_gpio_get_base(gpio, offset); in tegra186_gpio_direction_input()
228 if (WARN_ON(base == NULL)) in tegra186_gpio_direction_input()
229 return -ENODEV; in tegra186_gpio_direction_input()
231 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); in tegra186_gpio_direction_input()
233 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); in tegra186_gpio_direction_input()
235 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_direction_input()
238 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_direction_input()
247 void __iomem *base; in tegra186_gpio_direction_output() local
251 chip->set(chip, offset, level); in tegra186_gpio_direction_output()
253 base = tegra186_gpio_get_base(gpio, offset); in tegra186_gpio_direction_output()
254 if (WARN_ON(base == NULL)) in tegra186_gpio_direction_output()
255 return -EINVAL; in tegra186_gpio_direction_output()
258 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); in tegra186_gpio_direction_output()
260 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); in tegra186_gpio_direction_output()
262 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_direction_output()
265 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_direction_output()
276 void __iomem *base; in tegra186_gpio_en_hw_ts() local
280 return -EINVAL; in tegra186_gpio_en_hw_ts()
284 return -ENODEV; in tegra186_gpio_en_hw_ts()
286 base = tegra186_gpio_get_base(gpio, offset); in tegra186_gpio_en_hw_ts()
287 if (WARN_ON(base == NULL)) in tegra186_gpio_en_hw_ts()
288 return -EINVAL; in tegra186_gpio_en_hw_ts()
290 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_en_hw_ts()
302 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_en_hw_ts()
311 void __iomem *base; in tegra186_gpio_dis_hw_ts() local
315 return -EINVAL; in tegra186_gpio_dis_hw_ts()
319 return -ENODEV; in tegra186_gpio_dis_hw_ts()
321 base = tegra186_gpio_get_base(gpio, offset); in tegra186_gpio_dis_hw_ts()
322 if (WARN_ON(base == NULL)) in tegra186_gpio_dis_hw_ts()
323 return -EINVAL; in tegra186_gpio_dis_hw_ts()
325 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_dis_hw_ts()
335 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_dis_hw_ts()
343 void __iomem *base; in tegra186_gpio_get() local
346 base = tegra186_gpio_get_base(gpio, offset); in tegra186_gpio_get()
347 if (WARN_ON(base == NULL)) in tegra186_gpio_get()
348 return -ENODEV; in tegra186_gpio_get()
350 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_get()
352 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); in tegra186_gpio_get()
354 value = readl(base + TEGRA186_GPIO_INPUT); in tegra186_gpio_get()
363 void __iomem *base; in tegra186_gpio_set() local
366 base = tegra186_gpio_get_base(gpio, offset); in tegra186_gpio_set()
367 if (WARN_ON(base == NULL)) in tegra186_gpio_set()
370 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); in tegra186_gpio_set()
376 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE); in tegra186_gpio_set()
385 void __iomem *base; in tegra186_gpio_set_config() local
387 base = tegra186_gpio_get_base(gpio, offset); in tegra186_gpio_set_config()
388 if (base == NULL) in tegra186_gpio_set_config()
389 return -ENXIO; in tegra186_gpio_set_config()
392 return -ENOTSUPP; in tegra186_gpio_set_config()
401 return -EINVAL; in tegra186_gpio_set_config()
406 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL); in tegra186_gpio_set_config()
408 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_set_config()
410 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_gpio_set_config()
423 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0) in tegra186_gpio_add_pin_ranges()
426 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux); in tegra186_gpio_add_pin_ranges()
428 return -ENODEV; in tegra186_gpio_add_pin_ranges()
433 return -EPROBE_DEFER; in tegra186_gpio_add_pin_ranges()
435 for (i = 0; i < gpio->soc->num_pin_ranges; i++) { in tegra186_gpio_add_pin_ranges()
436 unsigned int pin = gpio->soc->pin_ranges[i].offset, port; in tegra186_gpio_add_pin_ranges() local
437 const char *group = gpio->soc->pin_ranges[i].group; in tegra186_gpio_add_pin_ranges()
439 port = pin / 8; in tegra186_gpio_add_pin_ranges()
442 if (port >= gpio->soc->num_ports) { in tegra186_gpio_add_pin_ranges()
443 dev_warn(chip->parent, "invalid port %u for %s\n", in tegra186_gpio_add_pin_ranges()
444 port, group); in tegra186_gpio_add_pin_ranges()
448 for (j = 0; j < port; j++) in tegra186_gpio_add_pin_ranges()
449 pin += gpio->soc->ports[j].pins; in tegra186_gpio_add_pin_ranges()
464 unsigned int port, pin, i, offset = 0; in tegra186_gpio_of_xlate() local
466 if (WARN_ON(chip->of_gpio_n_cells < 2)) in tegra186_gpio_of_xlate()
467 return -EINVAL; in tegra186_gpio_of_xlate()
469 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells)) in tegra186_gpio_of_xlate()
470 return -EINVAL; in tegra186_gpio_of_xlate()
472 port = spec->args[0] / 8; in tegra186_gpio_of_xlate()
473 pin = spec->args[0] % 8; in tegra186_gpio_of_xlate()
475 if (port >= gpio->soc->num_ports) { in tegra186_gpio_of_xlate()
476 dev_err(chip->parent, "invalid port number: %u\n", port); in tegra186_gpio_of_xlate()
477 return -EINVAL; in tegra186_gpio_of_xlate()
480 for (i = 0; i < port; i++) in tegra186_gpio_of_xlate()
481 offset += gpio->soc->ports[i].pins; in tegra186_gpio_of_xlate()
484 *flags = spec->args[1]; in tegra186_gpio_of_xlate()
495 void __iomem *base; in tegra186_irq_ack() local
497 base = tegra186_gpio_get_base(gpio, data->hwirq); in tegra186_irq_ack()
498 if (WARN_ON(base == NULL)) in tegra186_irq_ack()
501 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR); in tegra186_irq_ack()
508 void __iomem *base; in tegra186_irq_mask() local
511 base = tegra186_gpio_get_base(gpio, data->hwirq); in tegra186_irq_mask()
512 if (WARN_ON(base == NULL)) in tegra186_irq_mask()
515 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_irq_mask()
517 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_irq_mask()
519 gpiochip_disable_irq(&gpio->gpio, data->hwirq); in tegra186_irq_mask()
526 void __iomem *base; in tegra186_irq_unmask() local
529 base = tegra186_gpio_get_base(gpio, data->hwirq); in tegra186_irq_unmask()
530 if (WARN_ON(base == NULL)) in tegra186_irq_unmask()
533 gpiochip_enable_irq(&gpio->gpio, data->hwirq); in tegra186_irq_unmask()
535 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_irq_unmask()
537 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_irq_unmask()
544 void __iomem *base; in tegra186_irq_set_type() local
547 base = tegra186_gpio_get_base(gpio, data->hwirq); in tegra186_irq_set_type()
548 if (WARN_ON(base == NULL)) in tegra186_irq_set_type()
549 return -ENODEV; in tegra186_irq_set_type()
551 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_irq_set_type()
582 return -EINVAL; in tegra186_irq_set_type()
585 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); in tegra186_irq_set_type()
592 if (data->parent_data) in tegra186_irq_set_type()
600 if (data->parent_data) in tegra186_irq_set_wake()
610 seq_printf(p, dev_name(gc->parent)); in tegra186_irq_print_chip()
627 struct irq_domain *domain = gpio->gpio.irq.domain; in tegra186_gpio_irq()
634 for (i = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_irq()
635 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; in tegra186_gpio_irq() local
638 void __iomem *base; in tegra186_gpio_irq() local
640 base = gpio->base + port->bank * 0x1000 + port->port * 0x200; in tegra186_gpio_irq()
643 for (j = 0; j < gpio->num_irqs_per_bank; j++) { in tegra186_gpio_irq()
644 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j]) in tegra186_gpio_irq()
648 if (j == gpio->num_irqs_per_bank) in tegra186_gpio_irq()
651 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); in tegra186_gpio_irq()
653 for_each_set_bit(pin, &value, port->pins) { in tegra186_gpio_irq()
659 offset += port->pins; in tegra186_gpio_irq()
670 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data); in tegra186_gpio_irq_domain_translate()
671 unsigned int port, pin, i, offset = 0; in tegra186_gpio_irq_domain_translate() local
673 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2)) in tegra186_gpio_irq_domain_translate()
674 return -EINVAL; in tegra186_gpio_irq_domain_translate()
676 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells)) in tegra186_gpio_irq_domain_translate()
677 return -EINVAL; in tegra186_gpio_irq_domain_translate()
679 port = fwspec->param[0] / 8; in tegra186_gpio_irq_domain_translate()
680 pin = fwspec->param[0] % 8; in tegra186_gpio_irq_domain_translate()
682 if (port >= gpio->soc->num_ports) in tegra186_gpio_irq_domain_translate()
683 return -EINVAL; in tegra186_gpio_irq_domain_translate()
685 for (i = 0; i < port; i++) in tegra186_gpio_irq_domain_translate()
686 offset += gpio->soc->ports[i].pins; in tegra186_gpio_irq_domain_translate()
688 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; in tegra186_gpio_irq_domain_translate()
700 struct irq_fwspec *fwspec = &gfwspec->fwspec; in tegra186_gpio_populate_parent_fwspec()
702 fwspec->fwnode = chip->irq.parent_domain->fwnode; in tegra186_gpio_populate_parent_fwspec()
703 fwspec->param_count = 3; in tegra186_gpio_populate_parent_fwspec()
704 fwspec->param[0] = gpio->soc->instance; in tegra186_gpio_populate_parent_fwspec()
705 fwspec->param[1] = parent_hwirq; in tegra186_gpio_populate_parent_fwspec()
706 fwspec->param[2] = parent_type; in tegra186_gpio_populate_parent_fwspec()
717 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq); in tegra186_gpio_child_to_parent_hwirq()
729 for (i = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_child_offset_to_irq()
730 if (offset < gpio->soc->ports[i].pins) in tegra186_gpio_child_offset_to_irq()
733 offset -= gpio->soc->ports[i].pins; in tegra186_gpio_child_offset_to_irq()
740 { .compatible = "nvidia,tegra186-pmc" },
741 { .compatible = "nvidia,tegra194-pmc" },
742 { .compatible = "nvidia,tegra234-pmc" },
748 struct device *dev = gpio->gpio.parent; in tegra186_gpio_init_route_mapping()
752 for (i = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_init_route_mapping()
753 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; in tegra186_gpio_init_route_mapping() local
754 unsigned int offset, p = port->port; in tegra186_gpio_init_route_mapping()
755 void __iomem *base; in tegra186_gpio_init_route_mapping() local
757 base = gpio->secure + port->bank * 0x1000 + 0x800; in tegra186_gpio_init_route_mapping()
759 value = readl(base + TEGRA186_GPIO_CTL_SCR); in tegra186_gpio_init_route_mapping()
771 dev_dbg(dev, "programming default interrupt routing for port %s\n", in tegra186_gpio_init_route_mapping()
772 port->name); in tegra186_gpio_init_route_mapping()
785 value = readl(base + offset); in tegra186_gpio_init_route_mapping()
786 value = BIT(port->pins) - 1; in tegra186_gpio_init_route_mapping()
787 writel(value, base + offset); in tegra186_gpio_init_route_mapping()
794 struct device *dev = gpio->gpio.parent; in tegra186_gpio_irqs_per_bank()
796 if (gpio->num_irq > gpio->num_banks) { in tegra186_gpio_irqs_per_bank()
797 if (gpio->num_irq % gpio->num_banks != 0) in tegra186_gpio_irqs_per_bank()
801 if (gpio->num_irq < gpio->num_banks) in tegra186_gpio_irqs_per_bank()
804 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks; in tegra186_gpio_irqs_per_bank()
806 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank) in tegra186_gpio_irqs_per_bank()
813 gpio->num_irq, gpio->num_banks); in tegra186_gpio_irqs_per_bank()
814 return -EINVAL; in tegra186_gpio_irqs_per_bank()
826 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in tegra186_gpio_probe()
828 return -ENOMEM; in tegra186_gpio_probe()
830 gpio->soc = device_get_match_data(&pdev->dev); in tegra186_gpio_probe()
831 gpio->gpio.label = gpio->soc->name; in tegra186_gpio_probe()
832 gpio->gpio.parent = &pdev->dev; in tegra186_gpio_probe()
835 for (i = 0; i < gpio->soc->num_ports; i++) in tegra186_gpio_probe()
836 if (gpio->soc->ports[i].bank > gpio->num_banks) in tegra186_gpio_probe()
837 gpio->num_banks = gpio->soc->ports[i].bank; in tegra186_gpio_probe()
839 gpio->num_banks++; in tegra186_gpio_probe()
842 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security"); in tegra186_gpio_probe()
843 if (IS_ERR(gpio->secure)) { in tegra186_gpio_probe()
844 gpio->secure = devm_platform_ioremap_resource(pdev, 0); in tegra186_gpio_probe()
845 if (IS_ERR(gpio->secure)) in tegra186_gpio_probe()
846 return PTR_ERR(gpio->secure); in tegra186_gpio_probe()
849 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio"); in tegra186_gpio_probe()
850 if (IS_ERR(gpio->base)) { in tegra186_gpio_probe()
851 gpio->base = devm_platform_ioremap_resource(pdev, 1); in tegra186_gpio_probe()
852 if (IS_ERR(gpio->base)) in tegra186_gpio_probe()
853 return PTR_ERR(gpio->base); in tegra186_gpio_probe()
860 gpio->num_irq = err; in tegra186_gpio_probe()
866 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq), in tegra186_gpio_probe()
868 if (!gpio->irq) in tegra186_gpio_probe()
869 return -ENOMEM; in tegra186_gpio_probe()
871 for (i = 0; i < gpio->num_irq; i++) { in tegra186_gpio_probe()
876 gpio->irq[i] = err; in tegra186_gpio_probe()
879 gpio->gpio.request = gpiochip_generic_request; in tegra186_gpio_probe()
880 gpio->gpio.free = gpiochip_generic_free; in tegra186_gpio_probe()
881 gpio->gpio.get_direction = tegra186_gpio_get_direction; in tegra186_gpio_probe()
882 gpio->gpio.direction_input = tegra186_gpio_direction_input; in tegra186_gpio_probe()
883 gpio->gpio.direction_output = tegra186_gpio_direction_output; in tegra186_gpio_probe()
884 gpio->gpio.get = tegra186_gpio_get; in tegra186_gpio_probe()
885 gpio->gpio.set = tegra186_gpio_set; in tegra186_gpio_probe()
886 gpio->gpio.set_config = tegra186_gpio_set_config; in tegra186_gpio_probe()
887 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges; in tegra186_gpio_probe()
888 gpio->gpio.init_valid_mask = tegra186_init_valid_mask; in tegra186_gpio_probe()
889 if (gpio->soc->has_gte) { in tegra186_gpio_probe()
890 gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts; in tegra186_gpio_probe()
891 gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts; in tegra186_gpio_probe()
894 gpio->gpio.base = -1; in tegra186_gpio_probe()
896 for (i = 0; i < gpio->soc->num_ports; i++) in tegra186_gpio_probe()
897 gpio->gpio.ngpio += gpio->soc->ports[i].pins; in tegra186_gpio_probe()
899 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio, in tegra186_gpio_probe()
902 return -ENOMEM; in tegra186_gpio_probe()
904 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_probe()
905 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; in tegra186_gpio_probe() local
908 for (j = 0; j < port->pins; j++) { in tegra186_gpio_probe()
909 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, in tegra186_gpio_probe()
910 "P%s.%02x", port->name, j); in tegra186_gpio_probe()
912 return -ENOMEM; in tegra186_gpio_probe()
917 offset += port->pins; in tegra186_gpio_probe()
920 gpio->gpio.names = (const char * const *)names; in tegra186_gpio_probe()
923 gpio->gpio.of_gpio_n_cells = 2; in tegra186_gpio_probe()
924 gpio->gpio.of_xlate = tegra186_gpio_of_xlate; in tegra186_gpio_probe()
927 irq = &gpio->gpio.irq; in tegra186_gpio_probe()
929 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node); in tegra186_gpio_probe()
930 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq; in tegra186_gpio_probe()
931 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec; in tegra186_gpio_probe()
932 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq; in tegra186_gpio_probe()
933 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate; in tegra186_gpio_probe()
934 irq->handler = handle_simple_irq; in tegra186_gpio_probe()
935 irq->default_type = IRQ_TYPE_NONE; in tegra186_gpio_probe()
936 irq->parent_handler = tegra186_gpio_irq; in tegra186_gpio_probe()
937 irq->parent_handler_data = gpio; in tegra186_gpio_probe()
938 irq->num_parents = gpio->num_irq; in tegra186_gpio_probe()
947 if (gpio->num_irqs_per_bank > 1) { in tegra186_gpio_probe()
948 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks, in tegra186_gpio_probe()
949 sizeof(*irq->parents), GFP_KERNEL); in tegra186_gpio_probe()
950 if (!irq->parents) in tegra186_gpio_probe()
951 return -ENOMEM; in tegra186_gpio_probe()
953 for (i = 0; i < gpio->num_banks; i++) in tegra186_gpio_probe()
954 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank]; in tegra186_gpio_probe()
956 irq->num_parents = gpio->num_banks; in tegra186_gpio_probe()
958 irq->num_parents = gpio->num_irq; in tegra186_gpio_probe()
959 irq->parents = gpio->irq; in tegra186_gpio_probe()
962 if (gpio->soc->num_irqs_per_bank > 1) in tegra186_gpio_probe()
968 irq->parent_domain = irq_find_host(np); in tegra186_gpio_probe()
971 if (!irq->parent_domain) in tegra186_gpio_probe()
972 return -EPROBE_DEFER; in tegra186_gpio_probe()
978 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, in tegra186_gpio_probe()
979 sizeof(*irq->map), GFP_KERNEL); in tegra186_gpio_probe()
980 if (!irq->map) in tegra186_gpio_probe()
981 return -ENOMEM; in tegra186_gpio_probe()
983 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_probe()
984 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; in tegra186_gpio_probe() local
986 for (j = 0; j < port->pins; j++) in tegra186_gpio_probe()
987 irq->map[offset + j] = irq->parents[port->bank]; in tegra186_gpio_probe()
989 offset += port->pins; in tegra186_gpio_probe()
992 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); in tegra186_gpio_probe()
999 .port = _port, \
1032 .name = "tegra186-gpio",
1042 .port = _port, \
1060 .name = "tegra186-gpio-aon",
1070 .port = _port, \
1113 .name = "tegra194-gpio",
1118 .pinmux = "nvidia,tegra194-pinmux",
1126 .port = _port, \
1141 .name = "tegra194-gpio-aon",
1152 .port = _port, \
1187 .name = "tegra234-gpio",
1197 .port = _port, \
1213 .name = "tegra234-gpio-aon",
1224 .port = _port, \
1245 .name = "tegra241-gpio",
1255 .port = _port, \
1267 .name = "tegra241-gpio-aon",
1275 .compatible = "nvidia,tegra186-gpio",
1278 .compatible = "nvidia,tegra186-gpio-aon",
1281 .compatible = "nvidia,tegra194-gpio",
1284 .compatible = "nvidia,tegra194-gpio-aon",
1287 .compatible = "nvidia,tegra234-gpio",
1290 .compatible = "nvidia,tegra234-gpio-aon",
1311 .name = "tegra186-gpio",