1 // SPDX-License-Identifier: GPL-2.0-or-later
3  *  SYSCON GPIO driver
9 #include <linux/gpio/driver.h>
20 /* SYSCON driver is designed to use 32-bit wide registers */
25  * struct syscon_gpio_data - Configuration for the device.
32  * @dat_bit_offset:	Offset (in bits) to the first GPIO bit.
34  *			GPIO direction (Used with GPIO_SYSCON_FEAT_DIR flag).
62 	offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;  in syscon_gpio_get()
64 	ret = regmap_read(priv->syscon,  in syscon_gpio_get()
77 	offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;  in syscon_gpio_set()
79 	regmap_update_bits(priv->syscon,  in syscon_gpio_set()
89 	if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {  in syscon_gpio_dir_in()
92 		offs = priv->dir_reg_offset +  in syscon_gpio_dir_in()
93 		       priv->data->dir_bit_offset + offset;  in syscon_gpio_dir_in()
95 		regmap_update_bits(priv->syscon,  in syscon_gpio_dir_in()
107 	if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {  in syscon_gpio_dir_out()
110 		offs = priv->dir_reg_offset +  in syscon_gpio_dir_out()
111 		       priv->data->dir_bit_offset + offset;  in syscon_gpio_dir_out()
113 		regmap_update_bits(priv->syscon,  in syscon_gpio_dir_out()
119 	chip->set(chip, offset, val);  in syscon_gpio_dir_out()
125 	/* ARM CLPS711X SYSFLG1 Bits 8-10 */
140 	offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;  in rockchip_gpio_set()
143 	ret = regmap_write(priv->syscon,  in rockchip_gpio_set()
147 		dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);  in rockchip_gpio_set()
166 	offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;  in keystone_gpio_set()
172 			priv->syscon,  in keystone_gpio_set()
177 		dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);  in keystone_gpio_set()
181 	/* ARM Keystone 2 */
190 		.compatible	= "cirrus,ep7209-mctrl-gpio",
194 		.compatible	= "ti,keystone-dsp-gpio",
198 		.compatible	= "rockchip,rk3328-grf-gpio",
207 	struct device *dev = &pdev->dev;  in syscon_gpio_probe()
209 	struct device_node *np = dev->of_node;  in syscon_gpio_probe()
214 		return -ENOMEM;  in syscon_gpio_probe()
216 	priv->data = of_device_get_match_data(dev);  in syscon_gpio_probe()
218 	priv->syscon = syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev");  in syscon_gpio_probe()
219 	if (IS_ERR(priv->syscon) && np->parent)  in syscon_gpio_probe()
220 		priv->syscon = syscon_node_to_regmap(np->parent);  in syscon_gpio_probe()
221 	if (IS_ERR(priv->syscon))  in syscon_gpio_probe()
222 		return PTR_ERR(priv->syscon);  in syscon_gpio_probe()
224 	ret = of_property_read_u32_index(np, "gpio,syscon-dev", 1,  in syscon_gpio_probe()
225 					 &priv->dreg_offset);  in syscon_gpio_probe()
229 	priv->dreg_offset <<= 3;  in syscon_gpio_probe()
231 	ret = of_property_read_u32_index(np, "gpio,syscon-dev", 2,  in syscon_gpio_probe()
232 					 &priv->dir_reg_offset);  in syscon_gpio_probe()
236 	priv->dir_reg_offset <<= 3;  in syscon_gpio_probe()
238 	priv->chip.parent = dev;  in syscon_gpio_probe()
239 	priv->chip.owner = THIS_MODULE;  in syscon_gpio_probe()
240 	priv->chip.label = dev_name(dev);  in syscon_gpio_probe()
241 	priv->chip.base = -1;  in syscon_gpio_probe()
242 	priv->chip.ngpio = priv->data->bit_count;  in syscon_gpio_probe()
243 	priv->chip.get = syscon_gpio_get;  in syscon_gpio_probe()
244 	if (priv->data->flags & GPIO_SYSCON_FEAT_IN)  in syscon_gpio_probe()
245 		priv->chip.direction_input = syscon_gpio_dir_in;  in syscon_gpio_probe()
246 	if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) {  in syscon_gpio_probe()
247 		priv->chip.set = priv->data->set ? : syscon_gpio_set;  in syscon_gpio_probe()
248 		priv->chip.direction_output = syscon_gpio_dir_out;  in syscon_gpio_probe()
251 	return devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);  in syscon_gpio_probe()
256 		.name		= "gpio-syscon",
264 MODULE_DESCRIPTION("SYSCON GPIO driver");