Lines Matching +full:cortex +full:- +full:m3
1 // SPDX-License-Identifier: GPL-2.0
58 u32 val = readl_relaxed(ic->base + LPC18XX_GPIO_PIN_IC_ISEL); in lpc18xx_gpio_pin_ic_isel()
65 writel_relaxed(val, ic->base + LPC18XX_GPIO_PIN_IC_ISEL); in lpc18xx_gpio_pin_ic_isel()
71 writel_relaxed(BIT(pin), ic->base + reg); in lpc18xx_gpio_pin_ic_set()
76 struct lpc18xx_gpio_pin_ic *ic = d->chip_data; in lpc18xx_gpio_pin_ic_mask()
79 raw_spin_lock(&ic->lock); in lpc18xx_gpio_pin_ic_mask()
82 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_mask()
86 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_mask()
89 raw_spin_unlock(&ic->lock); in lpc18xx_gpio_pin_ic_mask()
96 struct lpc18xx_gpio_pin_ic *ic = d->chip_data; in lpc18xx_gpio_pin_ic_unmask()
99 raw_spin_lock(&ic->lock); in lpc18xx_gpio_pin_ic_unmask()
102 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_unmask()
106 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_unmask()
109 raw_spin_unlock(&ic->lock); in lpc18xx_gpio_pin_ic_unmask()
116 struct lpc18xx_gpio_pin_ic *ic = d->chip_data; in lpc18xx_gpio_pin_ic_eoi()
119 raw_spin_lock(&ic->lock); in lpc18xx_gpio_pin_ic_eoi()
122 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_eoi()
125 raw_spin_unlock(&ic->lock); in lpc18xx_gpio_pin_ic_eoi()
132 struct lpc18xx_gpio_pin_ic *ic = d->chip_data; in lpc18xx_gpio_pin_ic_set_type()
134 raw_spin_lock(&ic->lock); in lpc18xx_gpio_pin_ic_set_type()
137 lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, true); in lpc18xx_gpio_pin_ic_set_type()
138 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_set_type()
141 lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, true); in lpc18xx_gpio_pin_ic_set_type()
142 lpc18xx_gpio_pin_ic_set(ic, d->hwirq, in lpc18xx_gpio_pin_ic_set_type()
145 lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, false); in lpc18xx_gpio_pin_ic_set_type()
148 raw_spin_unlock(&ic->lock); in lpc18xx_gpio_pin_ic_set_type()
167 struct lpc18xx_gpio_pin_ic *ic = domain->host_data; in lpc18xx_gpio_pin_ic_domain_alloc()
172 return -EINVAL; in lpc18xx_gpio_pin_ic_domain_alloc()
174 hwirq = fwspec->param[0]; in lpc18xx_gpio_pin_ic_domain_alloc()
176 return -EINVAL; in lpc18xx_gpio_pin_ic_domain_alloc()
180 * into edge interrupts 32...39 on parent Cortex-M3/M4 NVIC in lpc18xx_gpio_pin_ic_domain_alloc()
182 parent_fwspec.fwnode = domain->parent->fwnode; in lpc18xx_gpio_pin_ic_domain_alloc()
205 struct device *dev = gc->gpio.parent; in lpc18xx_gpio_pin_ic_probe()
212 parent_node = of_irq_find_parent(dev->of_node); in lpc18xx_gpio_pin_ic_probe()
214 return -ENXIO; in lpc18xx_gpio_pin_ic_probe()
219 return -ENXIO; in lpc18xx_gpio_pin_ic_probe()
223 return -ENOMEM; in lpc18xx_gpio_pin_ic_probe()
225 index = of_property_match_string(dev->of_node, "reg-names", in lpc18xx_gpio_pin_ic_probe()
226 "gpio-pin-ic"); in lpc18xx_gpio_pin_ic_probe()
228 ret = -ENODEV; in lpc18xx_gpio_pin_ic_probe()
232 ret = of_address_to_resource(dev->of_node, index, &res); in lpc18xx_gpio_pin_ic_probe()
236 ic->base = devm_ioremap_resource(dev, &res); in lpc18xx_gpio_pin_ic_probe()
237 if (IS_ERR(ic->base)) { in lpc18xx_gpio_pin_ic_probe()
238 ret = PTR_ERR(ic->base); in lpc18xx_gpio_pin_ic_probe()
242 raw_spin_lock_init(&ic->lock); in lpc18xx_gpio_pin_ic_probe()
244 ic->domain = irq_domain_add_hierarchy(parent_domain, 0, in lpc18xx_gpio_pin_ic_probe()
246 dev->of_node, in lpc18xx_gpio_pin_ic_probe()
249 if (!ic->domain) { in lpc18xx_gpio_pin_ic_probe()
251 ret = -ENODEV; in lpc18xx_gpio_pin_ic_probe()
255 gc->pin_ic = ic; in lpc18xx_gpio_pin_ic_probe()
260 devm_iounmap(dev, ic->base); in lpc18xx_gpio_pin_ic_probe()
270 writeb(value ? 1 : 0, gc->base + offset); in lpc18xx_gpio_set()
276 return !!readb(gc->base + offset); in lpc18xx_gpio_get()
289 spin_lock_irqsave(&gc->lock, flags); in lpc18xx_gpio_direction()
290 dir = readl(gc->base + LPC18XX_REG_DIR(port)); in lpc18xx_gpio_direction()
295 writel(dir, gc->base + LPC18XX_REG_DIR(port)); in lpc18xx_gpio_direction()
296 spin_unlock_irqrestore(&gc->lock, flags); in lpc18xx_gpio_direction()
315 .label = "lpc18xx/43xx-gpio",
328 struct device *dev = &pdev->dev; in lpc18xx_gpio_probe()
334 return -ENOMEM; in lpc18xx_gpio_probe()
336 gc->gpio = lpc18xx_chip; in lpc18xx_gpio_probe()
339 index = of_property_match_string(dev->of_node, "reg-names", "gpio"); in lpc18xx_gpio_probe()
342 gc->base = devm_platform_ioremap_resource(pdev, 0); in lpc18xx_gpio_probe()
346 ret = of_address_to_resource(dev->of_node, index, &res); in lpc18xx_gpio_probe()
350 gc->base = devm_ioremap_resource(dev, &res); in lpc18xx_gpio_probe()
352 if (IS_ERR(gc->base)) in lpc18xx_gpio_probe()
353 return PTR_ERR(gc->base); in lpc18xx_gpio_probe()
355 gc->clk = devm_clk_get(dev, NULL); in lpc18xx_gpio_probe()
356 if (IS_ERR(gc->clk)) { in lpc18xx_gpio_probe()
358 return PTR_ERR(gc->clk); in lpc18xx_gpio_probe()
361 ret = clk_prepare_enable(gc->clk); in lpc18xx_gpio_probe()
367 spin_lock_init(&gc->lock); in lpc18xx_gpio_probe()
369 gc->gpio.parent = dev; in lpc18xx_gpio_probe()
371 ret = devm_gpiochip_add_data(dev, &gc->gpio, gc); in lpc18xx_gpio_probe()
374 clk_disable_unprepare(gc->clk); in lpc18xx_gpio_probe()
388 if (gc->pin_ic) in lpc18xx_gpio_remove()
389 irq_domain_remove(gc->pin_ic->domain); in lpc18xx_gpio_remove()
391 clk_disable_unprepare(gc->clk); in lpc18xx_gpio_remove()
395 { .compatible = "nxp,lpc1850-gpio" },
404 .name = "lpc18xx-gpio",