1 // SPDX-License-Identifier: GPL-2.0
6 // based on previous work and know-how from:
54  * struct ixp4xx_gpio - IXP4 GPIO state container
58  * @base: remapped I/O-memory base
59  * @irq_edge: Each bit represents an IRQ: 1: edge-triggered,
75 	__raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS);  in ixp4xx_gpio_irq_ack()
83 	gpiochip_disable_irq(gc, d->hwirq);  in ixp4xx_gpio_mask_irq()
91 	/* ACK when unmasking if not edge-triggered */  in ixp4xx_gpio_irq_unmask()
92 	if (!(g->irq_edge & BIT(d->hwirq)))  in ixp4xx_gpio_irq_unmask()
95 	gpiochip_enable_irq(gc, d->hwirq);  in ixp4xx_gpio_irq_unmask()
103 	int line = d->hwirq;  in ixp4xx_gpio_irq_set_type()
113 		g->irq_edge |= BIT(d->hwirq);  in ixp4xx_gpio_irq_set_type()
118 		g->irq_edge |= BIT(d->hwirq);  in ixp4xx_gpio_irq_set_type()
123 		g->irq_edge |= BIT(d->hwirq);  in ixp4xx_gpio_irq_set_type()
128 		g->irq_edge &= ~BIT(d->hwirq);  in ixp4xx_gpio_irq_set_type()
133 		g->irq_edge &= ~BIT(d->hwirq);  in ixp4xx_gpio_irq_set_type()
136 		return -EINVAL;  in ixp4xx_gpio_irq_set_type()
140 		/* pins 8-15 */  in ixp4xx_gpio_irq_set_type()
141 		line -= 8;  in ixp4xx_gpio_irq_set_type()
144 		/* pins 0-7 */  in ixp4xx_gpio_irq_set_type()
148 	raw_spin_lock_irqsave(&g->gc.bgpio_lock, flags);  in ixp4xx_gpio_irq_set_type()
151 	val = __raw_readl(g->base + int_reg);  in ixp4xx_gpio_irq_set_type()
153 	__raw_writel(val, g->base + int_reg);  in ixp4xx_gpio_irq_set_type()
155 	__raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS);  in ixp4xx_gpio_irq_set_type()
158 	val = __raw_readl(g->base + int_reg);  in ixp4xx_gpio_irq_set_type()
160 	__raw_writel(val, g->base + int_reg);  in ixp4xx_gpio_irq_set_type()
162 	/* Force-configure this line as an input */  in ixp4xx_gpio_irq_set_type()
163 	val = __raw_readl(g->base + IXP4XX_REG_GPOE);  in ixp4xx_gpio_irq_set_type()
164 	val |= BIT(d->hwirq);  in ixp4xx_gpio_irq_set_type()
165 	__raw_writel(val, g->base + IXP4XX_REG_GPOE);  in ixp4xx_gpio_irq_set_type()
167 	raw_spin_unlock_irqrestore(&g->gc.bgpio_lock, flags);  in ixp4xx_gpio_irq_set_type()
205 	return -EINVAL;  in ixp4xx_gpio_child_to_parent_hwirq()
211 	struct device *dev = &pdev->dev;  in ixp4xx_gpio_probe()
212 	struct device_node *np = dev->of_node;  in ixp4xx_gpio_probe()
223 		return -ENOMEM;  in ixp4xx_gpio_probe()
224 	g->dev = dev;  in ixp4xx_gpio_probe()
226 	g->base = devm_platform_ioremap_resource(pdev, 0);  in ixp4xx_gpio_probe()
227 	if (IS_ERR(g->base))  in ixp4xx_gpio_probe()
228 		return PTR_ERR(g->base);  in ixp4xx_gpio_probe()
233 		return -ENODEV;  in ixp4xx_gpio_probe()
238 		return -ENODEV;  in ixp4xx_gpio_probe()
240 	g->fwnode = of_node_to_fwnode(np);  in ixp4xx_gpio_probe()
252 	clk_14 = of_property_read_bool(np, "intel,ixp4xx-gpio14-clkout");  in ixp4xx_gpio_probe()
253 	clk_15 = of_property_read_bool(np, "intel,ixp4xx-gpio15-clkout");  in ixp4xx_gpio_probe()
259 	if (of_machine_is_compatible("dlink,dsm-g600-a") ||  in ixp4xx_gpio_probe()
260 	    of_machine_is_compatible("iom,nas-100d"))  in ixp4xx_gpio_probe()
263 		val = __raw_readl(g->base + IXP4XX_REG_GPCLK);  in ixp4xx_gpio_probe()
283 	__raw_writel(val, g->base + IXP4XX_REG_GPCLK);  in ixp4xx_gpio_probe()
286 	 * This is a very special big-endian ARM issue: when the IXP4xx is  in ixp4xx_gpio_probe()
288 	 * around to the CPU-native endianness. As you see mostly in the  in ixp4xx_gpio_probe()
301 	ret = bgpio_init(&g->gc, dev, 4,  in ixp4xx_gpio_probe()
302 			 g->base + IXP4XX_REG_GPIN,  in ixp4xx_gpio_probe()
303 			 g->base + IXP4XX_REG_GPOUT,  in ixp4xx_gpio_probe()
306 			 g->base + IXP4XX_REG_GPOE,  in ixp4xx_gpio_probe()
312 	g->gc.ngpio = 16;  in ixp4xx_gpio_probe()
313 	g->gc.label = "IXP4XX_GPIO_CHIP";  in ixp4xx_gpio_probe()
316 	 * are fetched using phandles, set this to -1 to get rid of  in ixp4xx_gpio_probe()
319 	g->gc.base = 0;  in ixp4xx_gpio_probe()
320 	g->gc.parent = &pdev->dev;  in ixp4xx_gpio_probe()
321 	g->gc.owner = THIS_MODULE;  in ixp4xx_gpio_probe()
323 	girq = &g->gc.irq;  in ixp4xx_gpio_probe()
325 	girq->fwnode = g->fwnode;  in ixp4xx_gpio_probe()
326 	girq->parent_domain = parent;  in ixp4xx_gpio_probe()
327 	girq->child_to_parent_hwirq = ixp4xx_gpio_child_to_parent_hwirq;  in ixp4xx_gpio_probe()
328 	girq->handler = handle_bad_irq;  in ixp4xx_gpio_probe()
329 	girq->default_type = IRQ_TYPE_NONE;  in ixp4xx_gpio_probe()
331 	ret = devm_gpiochip_add_data(dev, &g->gc, g);  in ixp4xx_gpio_probe()
345 		.compatible = "intel,ixp4xx-gpio",
353 		.name		= "ixp4xx-gpio",