Lines Matching +full:init +full:- +full:b +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
9 * linux/arch/arm/mach-ep93xx/core.c
12 #include <linux/init.h>
68 return egc->eic; in to_ep93xx_gpio_irq_chip()
72 * Interrupt handling for EP93xx on-chip GPIOs
85 writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); in ep93xx_gpio_update_int_params()
87 writeb_relaxed(eic->int_type2, in ep93xx_gpio_update_int_params()
88 epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET); in ep93xx_gpio_update_int_params()
90 writeb_relaxed(eic->int_type1, in ep93xx_gpio_update_int_params()
91 epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET); in ep93xx_gpio_update_int_params()
93 writeb_relaxed(eic->int_unmasked & eic->int_enabled, in ep93xx_gpio_update_int_params()
94 epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); in ep93xx_gpio_update_int_params()
105 eic->int_debounce |= port_mask; in ep93xx_gpio_int_debounce()
107 eic->int_debounce &= ~port_mask; in ep93xx_gpio_int_debounce()
109 writeb(eic->int_debounce, in ep93xx_gpio_int_debounce()
110 epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET); in ep93xx_gpio_int_debounce()
124 * Dispatch the IRQs to the irqdomain of each A and B in ep93xx_gpio_ab_irq_handler()
127 * between bank A and B and each has their own gpiochip. in ep93xx_gpio_ab_irq_handler()
129 stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS); in ep93xx_gpio_ab_irq_handler()
131 generic_handle_domain_irq(epg->gc[0].gc.irq.domain, in ep93xx_gpio_ab_irq_handler()
134 stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS); in ep93xx_gpio_ab_irq_handler()
136 generic_handle_domain_irq(epg->gc[1].gc.irq.domain, in ep93xx_gpio_ab_irq_handler()
147 * IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7} in ep93xx_gpio_f_irq_handler()
151 int port_f_idx = (irq & 7) ^ 4; /* {20..23,48..51} -> {0..7} */ in ep93xx_gpio_f_irq_handler()
164 int port_mask = BIT(d->irq & 7); in ep93xx_gpio_irq_ack()
167 eic->int_type2 ^= port_mask; /* switch edge direction */ in ep93xx_gpio_irq_ack()
171 writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET); in ep93xx_gpio_irq_ack()
179 int port_mask = BIT(d->irq & 7); in ep93xx_gpio_irq_mask_ack()
182 eic->int_type2 ^= port_mask; /* switch edge direction */ in ep93xx_gpio_irq_mask_ack()
184 eic->int_unmasked &= ~port_mask; in ep93xx_gpio_irq_mask_ack()
187 writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET); in ep93xx_gpio_irq_mask_ack()
197 eic->int_unmasked &= ~BIT(d->irq & 7); in ep93xx_gpio_irq_mask()
209 eic->int_unmasked |= BIT(d->irq & 7); in ep93xx_gpio_irq_unmask()
223 int offset = d->irq & 7; in ep93xx_gpio_irq_type()
227 gc->direction_input(gc, offset); in ep93xx_gpio_irq_type()
231 eic->int_type1 |= port_mask; in ep93xx_gpio_irq_type()
232 eic->int_type2 |= port_mask; in ep93xx_gpio_irq_type()
236 eic->int_type1 |= port_mask; in ep93xx_gpio_irq_type()
237 eic->int_type2 &= ~port_mask; in ep93xx_gpio_irq_type()
241 eic->int_type1 &= ~port_mask; in ep93xx_gpio_irq_type()
242 eic->int_type2 |= port_mask; in ep93xx_gpio_irq_type()
246 eic->int_type1 &= ~port_mask; in ep93xx_gpio_irq_type()
247 eic->int_type2 &= ~port_mask; in ep93xx_gpio_irq_type()
251 eic->int_type1 |= port_mask; in ep93xx_gpio_irq_type()
253 if (gc->get(gc, offset)) in ep93xx_gpio_irq_type()
254 eic->int_type2 &= ~port_mask; /* falling */ in ep93xx_gpio_irq_type()
256 eic->int_type2 |= port_mask; /* rising */ in ep93xx_gpio_irq_type()
260 return -EINVAL; in ep93xx_gpio_irq_type()
265 eic->int_enabled |= port_mask; in ep93xx_gpio_irq_type()
273 * gpiolib interface for EP93xx on-chip GPIOs
301 /* Bank B has 8 IRQs */
302 EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, EP93XX_GPIO_B_IRQ_BASE),
318 return -ENOTSUPP; in ep93xx_gpio_set_config()
330 seq_printf(p, dev_name(gc->parent)); in ep93xx_irq_print_chip()
334 .name = "ep93xx-gpio-eic",
350 void __iomem *data = epg->base + bank->data; in ep93xx_gpio_add_bank()
351 void __iomem *dir = epg->base + bank->dir; in ep93xx_gpio_add_bank()
352 struct gpio_chip *gc = &egc->gc; in ep93xx_gpio_add_bank()
353 struct device *dev = &pdev->dev; in ep93xx_gpio_add_bank()
361 gc->label = bank->label; in ep93xx_gpio_add_bank()
362 gc->base = bank->base; in ep93xx_gpio_add_bank()
364 girq = &gc->irq; in ep93xx_gpio_add_bank()
365 if (bank->has_irq || bank->has_hierarchical_irq) { in ep93xx_gpio_add_bank()
366 gc->set_config = ep93xx_gpio_set_config; in ep93xx_gpio_add_bank()
367 egc->eic = devm_kcalloc(dev, 1, in ep93xx_gpio_add_bank()
368 sizeof(*egc->eic), in ep93xx_gpio_add_bank()
370 if (!egc->eic) in ep93xx_gpio_add_bank()
371 return -ENOMEM; in ep93xx_gpio_add_bank()
372 egc->eic->irq_offset = bank->irq; in ep93xx_gpio_add_bank()
376 if (bank->has_irq) { in ep93xx_gpio_add_bank()
379 girq->parent_handler = ep93xx_gpio_ab_irq_handler; in ep93xx_gpio_add_bank()
380 girq->num_parents = 1; in ep93xx_gpio_add_bank()
381 girq->parents = devm_kcalloc(dev, girq->num_parents, in ep93xx_gpio_add_bank()
382 sizeof(*girq->parents), in ep93xx_gpio_add_bank()
384 if (!girq->parents) in ep93xx_gpio_add_bank()
385 return -ENOMEM; in ep93xx_gpio_add_bank()
386 girq->default_type = IRQ_TYPE_NONE; in ep93xx_gpio_add_bank()
387 girq->handler = handle_level_irq; in ep93xx_gpio_add_bank()
388 girq->parents[0] = ab_parent_irq; in ep93xx_gpio_add_bank()
389 girq->first = bank->irq_base; in ep93xx_gpio_add_bank()
393 if (bank->has_hierarchical_irq) { in ep93xx_gpio_add_bank()
401 girq->parent_handler = ep93xx_gpio_f_irq_handler; in ep93xx_gpio_add_bank()
402 girq->num_parents = 8; in ep93xx_gpio_add_bank()
403 girq->parents = devm_kcalloc(dev, girq->num_parents, in ep93xx_gpio_add_bank()
404 sizeof(*girq->parents), in ep93xx_gpio_add_bank()
406 if (!girq->parents) in ep93xx_gpio_add_bank()
407 return -ENOMEM; in ep93xx_gpio_add_bank()
409 for (i = 0; i < girq->num_parents; i++) { in ep93xx_gpio_add_bank()
410 girq->parents[i] = platform_get_irq(pdev, i + 1); in ep93xx_gpio_add_bank()
411 gpio_irq = bank->irq_base + i; in ep93xx_gpio_add_bank()
412 irq_set_chip_data(gpio_irq, &epg->gc[5]); in ep93xx_gpio_add_bank()
414 girq->chip, in ep93xx_gpio_add_bank()
418 girq->default_type = IRQ_TYPE_NONE; in ep93xx_gpio_add_bank()
419 girq->handler = handle_level_irq; in ep93xx_gpio_add_bank()
420 girq->first = bank->irq_base; in ep93xx_gpio_add_bank()
431 epg = devm_kzalloc(&pdev->dev, sizeof(*epg), GFP_KERNEL); in ep93xx_gpio_probe()
433 return -ENOMEM; in ep93xx_gpio_probe()
435 epg->base = devm_platform_ioremap_resource(pdev, 0); in ep93xx_gpio_probe()
436 if (IS_ERR(epg->base)) in ep93xx_gpio_probe()
437 return PTR_ERR(epg->base); in ep93xx_gpio_probe()
440 struct ep93xx_gpio_chip *gc = &epg->gc[i]; in ep93xx_gpio_probe()
444 dev_warn(&pdev->dev, "Unable to add gpio bank %s\n", in ep93xx_gpio_probe()
445 bank->label); in ep93xx_gpio_probe()
453 .name = "gpio-ep93xx",