148 static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset,  in sprd_eic_update()  argument
153 		sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);  in sprd_eic_update()
161 		tmp |= BIT(SPRD_EIC_BIT(offset));  in sprd_eic_update()
163 		tmp &= ~BIT(SPRD_EIC_BIT(offset));  in sprd_eic_update()
169 static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg)  in sprd_eic_read()  argument
173 		sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);  in sprd_eic_read()
175 	return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset)));  in sprd_eic_read()
178 static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset)  in sprd_eic_request()  argument
180 	sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1);  in sprd_eic_request()
184 static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset)  in sprd_eic_free()  argument
186 	sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0);  in sprd_eic_free()
189 static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset)  in sprd_eic_get()  argument
195 		return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA);  in sprd_eic_get()
197 		return sprd_eic_read(chip, offset, SPRD_EIC_ASYNC_DATA);  in sprd_eic_get()
199 		return sprd_eic_read(chip, offset, SPRD_EIC_SYNC_DATA);  in sprd_eic_get()
205 static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset)  in sprd_eic_direction_input()  argument
211 static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value)  in sprd_eic_set()  argument
216 static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset,  in sprd_eic_set_debounce()  argument
221 		sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);  in sprd_eic_set_debounce()
222 	u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4;  in sprd_eic_set_debounce()
231 static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset,  in sprd_eic_set_config()  argument
238 		return sprd_eic_set_debounce(chip, offset, arg);  in sprd_eic_set_config()
247 	u32 offset = irqd_to_hwirq(data);  in sprd_eic_irq_mask()  local
251 		sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0);  in sprd_eic_irq_mask()
252 		sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0);  in sprd_eic_irq_mask()
255 		sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0);  in sprd_eic_irq_mask()
258 		sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0);  in sprd_eic_irq_mask()
261 		sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0);  in sprd_eic_irq_mask()
267 	gpiochip_disable_irq(chip, offset);  in sprd_eic_irq_mask()
274 	u32 offset = irqd_to_hwirq(data);  in sprd_eic_irq_unmask()  local
276 	gpiochip_enable_irq(chip, offset);  in sprd_eic_irq_unmask()
280 		sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1);  in sprd_eic_irq_unmask()
281 		sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1);  in sprd_eic_irq_unmask()
284 		sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1);  in sprd_eic_irq_unmask()
287 		sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1);  in sprd_eic_irq_unmask()
290 		sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1);  in sprd_eic_irq_unmask()
301 	u32 offset = irqd_to_hwirq(data);  in sprd_eic_irq_ack()  local
305 		sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);  in sprd_eic_irq_ack()
308 		sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);  in sprd_eic_irq_ack()
311 		sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);  in sprd_eic_irq_ack()
314 		sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);  in sprd_eic_irq_ack()
325 	u32 offset = irqd_to_hwirq(data);  in sprd_eic_irq_set_type()  local
332 			sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);  in sprd_eic_irq_set_type()
333 			sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);  in sprd_eic_irq_set_type()
336 			sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);  in sprd_eic_irq_set_type()
337 			sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);  in sprd_eic_irq_set_type()
342 			state = sprd_eic_get(chip, offset);  in sprd_eic_irq_set_type()
344 				sprd_eic_update(chip, offset,  in sprd_eic_irq_set_type()
346 				sprd_eic_update(chip, offset,  in sprd_eic_irq_set_type()
349 				sprd_eic_update(chip, offset,  in sprd_eic_irq_set_type()
351 				sprd_eic_update(chip, offset,  in sprd_eic_irq_set_type()
364 			sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);  in sprd_eic_irq_set_type()
365 			sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);  in sprd_eic_irq_set_type()
368 			sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);  in sprd_eic_irq_set_type()
369 			sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);  in sprd_eic_irq_set_type()
374 			state = sprd_eic_get(chip, offset);  in sprd_eic_irq_set_type()
376 				sprd_eic_update(chip, offset,  in sprd_eic_irq_set_type()
378 				sprd_eic_update(chip, offset,  in sprd_eic_irq_set_type()
381 				sprd_eic_update(chip, offset,  in sprd_eic_irq_set_type()
383 				sprd_eic_update(chip, offset,  in sprd_eic_irq_set_type()
396 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);  in sprd_eic_irq_set_type()
397 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);  in sprd_eic_irq_set_type()
398 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);  in sprd_eic_irq_set_type()
399 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);  in sprd_eic_irq_set_type()
403 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);  in sprd_eic_irq_set_type()
404 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);  in sprd_eic_irq_set_type()
405 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);  in sprd_eic_irq_set_type()
406 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);  in sprd_eic_irq_set_type()
410 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);  in sprd_eic_irq_set_type()
411 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1);  in sprd_eic_irq_set_type()
412 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);  in sprd_eic_irq_set_type()
416 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);  in sprd_eic_irq_set_type()
417 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);  in sprd_eic_irq_set_type()
418 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);  in sprd_eic_irq_set_type()
419 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);  in sprd_eic_irq_set_type()
423 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);  in sprd_eic_irq_set_type()
424 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);  in sprd_eic_irq_set_type()
425 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);  in sprd_eic_irq_set_type()
426 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);  in sprd_eic_irq_set_type()
436 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);  in sprd_eic_irq_set_type()
437 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);  in sprd_eic_irq_set_type()
438 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);  in sprd_eic_irq_set_type()
439 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);  in sprd_eic_irq_set_type()
443 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);  in sprd_eic_irq_set_type()
444 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);  in sprd_eic_irq_set_type()
445 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);  in sprd_eic_irq_set_type()
446 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);  in sprd_eic_irq_set_type()
450 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);  in sprd_eic_irq_set_type()
451 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1);  in sprd_eic_irq_set_type()
452 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);  in sprd_eic_irq_set_type()
456 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);  in sprd_eic_irq_set_type()
457 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);  in sprd_eic_irq_set_type()
458 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);  in sprd_eic_irq_set_type()
459 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);  in sprd_eic_irq_set_type()
463 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);  in sprd_eic_irq_set_type()
464 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);  in sprd_eic_irq_set_type()
465 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);  in sprd_eic_irq_set_type()
466 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);  in sprd_eic_irq_set_type()
482 				    unsigned int offset)  in sprd_eic_toggle_trigger()  argument
499 	state = sprd_eic_get(chip, offset);  in sprd_eic_toggle_trigger()
505 			sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);  in sprd_eic_toggle_trigger()
507 			sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);  in sprd_eic_toggle_trigger()
511 			sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);  in sprd_eic_toggle_trigger()
513 			sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);  in sprd_eic_toggle_trigger()
520 	post_state = sprd_eic_get(chip, offset);  in sprd_eic_toggle_trigger()
562 			u32 offset = bank * SPRD_EIC_PER_BANK_NR + n;  in sprd_eic_handle_one_type()  local
564 			girq = irq_find_mapping(chip->irq.domain, offset);  in sprd_eic_handle_one_type()
567 			sprd_eic_toggle_trigger(chip, girq, offset);  in sprd_eic_handle_one_type()