Lines Matching full:g
75 struct davinci_gpio_regs __iomem *g; in irq2regs() local
77 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d); in irq2regs()
79 return g; in irq2regs()
91 struct davinci_gpio_regs __iomem *g; in __davinci_direction() local
97 g = d->regs[bank]; in __davinci_direction()
99 temp = readl_relaxed(&g->dir); in __davinci_direction()
102 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); in __davinci_direction()
106 writel_relaxed(temp, &g->dir); in __davinci_direction()
133 struct davinci_gpio_regs __iomem *g; in davinci_gpio_get() local
136 g = d->regs[bank]; in davinci_gpio_get()
138 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data)); in davinci_gpio_get()
148 struct davinci_gpio_regs __iomem *g; in davinci_gpio_set() local
151 g = d->regs[bank]; in davinci_gpio_set()
154 value ? &g->set_data : &g->clr_data); in davinci_gpio_set()
289 struct davinci_gpio_regs __iomem *g = irq2regs(d); in gpio_irq_disable() local
292 writel_relaxed(mask, &g->clr_falling); in gpio_irq_disable()
293 writel_relaxed(mask, &g->clr_rising); in gpio_irq_disable()
298 struct davinci_gpio_regs __iomem *g = irq2regs(d); in gpio_irq_enable() local
307 writel_relaxed(mask, &g->set_falling); in gpio_irq_enable()
309 writel_relaxed(mask, &g->set_rising); in gpio_irq_enable()
330 struct davinci_gpio_regs __iomem *g; in gpio_irq_handler() local
338 g = irqdata->regs; in gpio_irq_handler()
353 status = readl_relaxed(&g->intstat) & mask; in gpio_irq_handler()
356 writel_relaxed(status, &g->intstat); in gpio_irq_handler()
402 struct davinci_gpio_regs __iomem *g; in gpio_irq_type_unbanked() local
406 g = (struct davinci_gpio_regs __iomem *)d->regs[0]; in gpio_irq_type_unbanked()
420 ? &g->set_falling : &g->clr_falling); in gpio_irq_type_unbanked()
422 ? &g->set_rising : &g->clr_rising); in gpio_irq_type_unbanked()
433 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32]; in davinci_gpio_irq_map() local
438 irq_set_chip_data(irq, (__force void *)g); in davinci_gpio_irq_map()
487 struct davinci_gpio_regs __iomem *g; in davinci_gpio_irq_setup() local
557 g = chips->regs[0]; in davinci_gpio_irq_setup()
558 writel_relaxed(~0, &g->set_falling); in davinci_gpio_irq_setup()
559 writel_relaxed(~0, &g->set_rising); in davinci_gpio_irq_setup()
581 g = chips->regs[bank / 2]; in davinci_gpio_irq_setup()
582 writel_relaxed(~0, &g->clr_falling); in davinci_gpio_irq_setup()
583 writel_relaxed(~0, &g->clr_rising); in davinci_gpio_irq_setup()
599 irqdata->regs = g; in davinci_gpio_irq_setup()
622 struct davinci_gpio_regs __iomem *g; in davinci_gpio_save_context() local
631 g = chips->regs[bank]; in davinci_gpio_save_context()
633 context->dir = readl_relaxed(&g->dir); in davinci_gpio_save_context()
634 context->set_data = readl_relaxed(&g->set_data); in davinci_gpio_save_context()
635 context->set_rising = readl_relaxed(&g->set_rising); in davinci_gpio_save_context()
636 context->set_falling = readl_relaxed(&g->set_falling); in davinci_gpio_save_context()
640 writel_relaxed(GENMASK(31, 0), &g->intstat); in davinci_gpio_save_context()
646 struct davinci_gpio_regs __iomem *g; in davinci_gpio_restore_context() local
657 g = chips->regs[bank]; in davinci_gpio_restore_context()
659 if (readl_relaxed(&g->dir) != context->dir) in davinci_gpio_restore_context()
660 writel_relaxed(context->dir, &g->dir); in davinci_gpio_restore_context()
661 if (readl_relaxed(&g->set_data) != context->set_data) in davinci_gpio_restore_context()
662 writel_relaxed(context->set_data, &g->set_data); in davinci_gpio_restore_context()
663 if (readl_relaxed(&g->set_rising) != context->set_rising) in davinci_gpio_restore_context()
664 writel_relaxed(context->set_rising, &g->set_rising); in davinci_gpio_restore_context()
665 if (readl_relaxed(&g->set_falling) != context->set_falling) in davinci_gpio_restore_context()
666 writel_relaxed(context->set_falling, &g->set_falling); in davinci_gpio_restore_context()