Lines Matching +full:four +full:- +full:bank
1 // SPDX-License-Identifier: GPL-2.0-or-later
34 unsigned int bank; member
48 * The @timer_users has four elements but the first element is unused. This is
211 const struct aspeed_gpio_bank *bank, in bank_reg() argument
216 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
218 return gpio->base + bank->rdata_reg; in bank_reg()
220 return gpio->base + bank->val_regs + GPIO_VAL_DIR; in bank_reg()
222 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
224 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
226 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
228 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in bank_reg()
230 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in bank_reg()
232 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1; in bank_reg()
234 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2; in bank_reg()
236 return gpio->base + bank->tolerance_regs; in bank_reg()
238 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0; in bank_reg()
240 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1; in bank_reg()
255 unsigned int bank = GPIO_BANK(offset); in to_bank() local
257 WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks)); in to_bank()
258 return &aspeed_gpio_banks[bank]; in to_bank()
263 return !(props->input || props->output); in is_bank_props_sentinel()
269 const struct aspeed_bank_props *props = gpio->config->props; in find_bank_props()
272 if (props->bank == GPIO_BANK(offset)) in find_bank_props()
283 const struct aspeed_gpio_bank *bank = to_bank(offset); in have_gpio() local
286 return bank->names[group][0] != '\0' && in have_gpio()
287 (!props || ((props->input | props->output) & GPIO_BIT(offset))); in have_gpio()
294 return !props || (props->input & GPIO_BIT(offset)); in have_input()
304 return !props || (props->output & GPIO_BIT(offset)); in have_output()
308 const struct aspeed_gpio_bank *bank, in aspeed_gpio_change_cmd_source() argument
311 void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0); in aspeed_gpio_change_cmd_source()
312 void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1); in aspeed_gpio_change_cmd_source()
317 * bits of the bank index, and use them to select the in aspeed_gpio_change_cmd_source()
342 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_copro_request() local
344 if (!copro_ops || !gpio->cf_copro_bankmap) in aspeed_gpio_copro_request()
346 if (!gpio->cf_copro_bankmap[offset >> 3]) in aspeed_gpio_copro_request()
348 if (!copro_ops->request_access) in aspeed_gpio_copro_request()
352 copro_ops->request_access(copro_data); in aspeed_gpio_copro_request()
355 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, GPIO_CMDSRC_ARM); in aspeed_gpio_copro_request()
358 gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata)); in aspeed_gpio_copro_request()
366 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_copro_release() local
368 if (!copro_ops || !gpio->cf_copro_bankmap) in aspeed_gpio_copro_release()
370 if (!gpio->cf_copro_bankmap[offset >> 3]) in aspeed_gpio_copro_release()
372 if (!copro_ops->release_access) in aspeed_gpio_copro_release()
376 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, in aspeed_gpio_copro_release()
380 copro_ops->release_access(copro_data); in aspeed_gpio_copro_release()
386 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_get() local
388 return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset)); in aspeed_gpio_get()
395 const struct aspeed_gpio_bank *bank = to_bank(offset); in __aspeed_gpio_set() local
399 addr = bank_reg(gpio, bank, reg_val); in __aspeed_gpio_set()
400 reg = gpio->dcache[GPIO_BANK(offset)]; in __aspeed_gpio_set()
406 gpio->dcache[GPIO_BANK(offset)] = reg; in __aspeed_gpio_set()
418 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_set()
425 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_set()
431 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_dir_in() local
432 void __iomem *addr = bank_reg(gpio, bank, reg_dir); in aspeed_gpio_dir_in()
438 return -ENOTSUPP; in aspeed_gpio_dir_in()
440 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_dir_in()
450 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_dir_in()
459 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_dir_out() local
460 void __iomem *addr = bank_reg(gpio, bank, reg_dir); in aspeed_gpio_dir_out()
466 return -ENOTSUPP; in aspeed_gpio_dir_out()
468 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_dir_out()
479 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_dir_out()
487 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_get_direction() local
497 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_get_direction()
499 val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset); in aspeed_gpio_get_direction()
501 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_get_direction()
508 const struct aspeed_gpio_bank **bank, in irqd_to_aspeed_gpio_data() argument
519 return -ENOTSUPP; in irqd_to_aspeed_gpio_data()
522 *bank = to_bank(*offset); in irqd_to_aspeed_gpio_data()
530 const struct aspeed_gpio_bank *bank; in aspeed_gpio_irq_ack() local
538 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_gpio_irq_ack()
542 status_addr = bank_reg(gpio, bank, reg_irq_status); in aspeed_gpio_irq_ack()
544 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_irq_ack()
551 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_irq_ack()
556 const struct aspeed_gpio_bank *bank; in aspeed_gpio_irq_set_mask() local
564 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_gpio_irq_set_mask()
568 addr = bank_reg(gpio, bank, reg_irq_enable); in aspeed_gpio_irq_set_mask()
572 gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d)); in aspeed_gpio_irq_set_mask()
574 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_irq_set_mask()
586 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_irq_set_mask()
590 gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(d)); in aspeed_gpio_irq_set_mask()
609 const struct aspeed_gpio_bank *bank; in aspeed_gpio_set_type() local
617 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_gpio_set_type()
619 return -EINVAL; in aspeed_gpio_set_type()
639 return -EINVAL; in aspeed_gpio_set_type()
642 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_set_type()
645 addr = bank_reg(gpio, bank, reg_irq_type0); in aspeed_gpio_set_type()
650 addr = bank_reg(gpio, bank, reg_irq_type1); in aspeed_gpio_set_type()
655 addr = bank_reg(gpio, bank, reg_irq_type2); in aspeed_gpio_set_type()
662 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_set_type()
680 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); in aspeed_gpio_irq_handler()
682 const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i]; in aspeed_gpio_irq_handler() local
684 reg = ioread32(bank_reg(data, bank, reg_irq_status)); in aspeed_gpio_irq_handler()
687 generic_handle_domain_irq(gc->irq.domain, i * 32 + p); in aspeed_gpio_irq_handler()
698 const struct aspeed_bank_props *props = gpio->config->props; in aspeed_init_irq_valid_mask()
702 const unsigned long int input = props->input; in aspeed_init_irq_valid_mask()
706 unsigned int i = props->bank * 32 + offset; in aspeed_init_irq_valid_mask()
708 if (i >= gpio->chip.ngpio) in aspeed_init_irq_valid_mask()
729 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_reset_tolerance()
743 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_reset_tolerance()
751 return -ENODEV; in aspeed_gpio_request()
768 rate = clk_get_rate(gpio->clk); in usecs_to_cycles()
770 return -ENOTSUPP; in usecs_to_cycles()
776 return -ERANGE; in usecs_to_cycles()
784 /* Call under gpio->lock */
788 if (WARN(gpio->offset_timer[offset] != 0, in register_allocated_timer()
790 offset, gpio->offset_timer[offset])) in register_allocated_timer()
791 return -EINVAL; in register_allocated_timer()
793 if (WARN(gpio->timer_users[timer] == UINT_MAX, in register_allocated_timer()
795 return -EPERM; in register_allocated_timer()
797 gpio->offset_timer[offset] = timer; in register_allocated_timer()
798 gpio->timer_users[timer]++; in register_allocated_timer()
803 /* Call under gpio->lock */
807 if (WARN(gpio->offset_timer[offset] == 0, in unregister_allocated_timer()
809 return -EINVAL; in unregister_allocated_timer()
811 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0, in unregister_allocated_timer()
813 gpio->offset_timer[offset])) in unregister_allocated_timer()
814 return -EINVAL; in unregister_allocated_timer()
816 gpio->timer_users[gpio->offset_timer[offset]]--; in unregister_allocated_timer()
817 gpio->offset_timer[offset] = 0; in unregister_allocated_timer()
822 /* Call under gpio->lock */
826 return gpio->offset_timer[offset] > 0; in timer_allocation_registered()
829 /* Call under gpio->lock */
833 const struct aspeed_gpio_bank *bank = to_bank(offset); in configure_timer() local
841 addr = bank_reg(gpio, bank, reg_debounce_sel1); in configure_timer()
845 addr = bank_reg(gpio, bank, reg_debounce_sel2); in configure_timer()
859 if (!gpio->clk) in enable_debounce()
860 return -EINVAL; in enable_debounce()
864 dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n", in enable_debounce()
865 usecs, clk_get_rate(gpio->clk), rc); in enable_debounce()
869 raw_spin_lock_irqsave(&gpio->lock, flags); in enable_debounce()
881 cycles = ioread32(gpio->base + debounce_timers[i]); in enable_debounce()
893 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) { in enable_debounce()
894 if (gpio->timer_users[j] == 0) in enable_debounce()
898 if (j == ARRAY_SIZE(gpio->timer_users)) { in enable_debounce()
899 dev_warn(chip->parent, in enable_debounce()
903 rc = -EPERM; in enable_debounce()
917 iowrite32(requested_cycles, gpio->base + debounce_timers[i]); in enable_debounce()
921 rc = -EINVAL; in enable_debounce()
929 raw_spin_unlock_irqrestore(&gpio->lock, flags); in enable_debounce()
940 raw_spin_lock_irqsave(&gpio->lock, flags); in disable_debounce()
946 raw_spin_unlock_irqrestore(&gpio->lock, flags); in disable_debounce()
957 return -ENOTSUPP; in set_debounce()
979 /* Return -ENOTSUPP to trigger emulation, as per datasheet */ in aspeed_gpio_set_config()
980 return -ENOTSUPP; in aspeed_gpio_set_config()
984 return -ENOTSUPP; in aspeed_gpio_set_config()
988 * aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with
1003 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire
1004 * bank gets marked and any access from the ARM will
1007 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space
1008 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space
1009 * @bit: If non-NULL, returns the bit number of the GPIO in the registers
1017 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_copro_grab_gpio() local
1020 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_grab_gpio()
1021 gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL); in aspeed_gpio_copro_grab_gpio()
1022 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_grab_gpio()
1023 return -ENOMEM; in aspeed_gpio_copro_grab_gpio()
1024 if (offset < 0 || offset > gpio->chip.ngpio) in aspeed_gpio_copro_grab_gpio()
1025 return -EINVAL; in aspeed_gpio_copro_grab_gpio()
1028 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_copro_grab_gpio()
1031 if (gpio->cf_copro_bankmap[bindex] == 0xff) { in aspeed_gpio_copro_grab_gpio()
1032 rc = -EIO; in aspeed_gpio_copro_grab_gpio()
1035 gpio->cf_copro_bankmap[bindex]++; in aspeed_gpio_copro_grab_gpio()
1038 if (gpio->cf_copro_bankmap[bindex] == 1) in aspeed_gpio_copro_grab_gpio()
1039 aspeed_gpio_change_cmd_source(gpio, bank, bindex, in aspeed_gpio_copro_grab_gpio()
1043 *vreg_offset = bank->val_regs; in aspeed_gpio_copro_grab_gpio()
1045 *dreg_offset = bank->rdata_reg; in aspeed_gpio_copro_grab_gpio()
1049 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_copro_grab_gpio()
1055 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor.
1063 const struct aspeed_gpio_bank *bank = to_bank(offset); in aspeed_gpio_copro_release_gpio() local
1066 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_release_gpio()
1067 return -ENXIO; in aspeed_gpio_copro_release_gpio()
1069 if (offset < 0 || offset > gpio->chip.ngpio) in aspeed_gpio_copro_release_gpio()
1070 return -EINVAL; in aspeed_gpio_copro_release_gpio()
1073 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_copro_release_gpio()
1076 if (gpio->cf_copro_bankmap[bindex] == 0) { in aspeed_gpio_copro_release_gpio()
1077 rc = -EIO; in aspeed_gpio_copro_release_gpio()
1080 gpio->cf_copro_bankmap[bindex]--; in aspeed_gpio_copro_release_gpio()
1083 if (gpio->cf_copro_bankmap[bindex] == 0) in aspeed_gpio_copro_release_gpio()
1084 aspeed_gpio_change_cmd_source(gpio, bank, bindex, in aspeed_gpio_copro_release_gpio()
1087 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_copro_release_gpio()
1094 const struct aspeed_gpio_bank *bank; in aspeed_gpio_irq_print_chip() local
1099 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_gpio_irq_print_chip()
1103 seq_printf(p, dev_name(gpio->dev)); in aspeed_gpio_irq_print_chip()
1126 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
1131 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
1137 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
1143 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
1163 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
1164 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
1165 { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, },
1178 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in aspeed_gpio_probe()
1180 return -ENOMEM; in aspeed_gpio_probe()
1182 gpio->base = devm_platform_ioremap_resource(pdev, 0); in aspeed_gpio_probe()
1183 if (IS_ERR(gpio->base)) in aspeed_gpio_probe()
1184 return PTR_ERR(gpio->base); in aspeed_gpio_probe()
1186 gpio->dev = &pdev->dev; in aspeed_gpio_probe()
1188 raw_spin_lock_init(&gpio->lock); in aspeed_gpio_probe()
1190 gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); in aspeed_gpio_probe()
1192 return -EINVAL; in aspeed_gpio_probe()
1194 gpio->clk = of_clk_get(pdev->dev.of_node, 0); in aspeed_gpio_probe()
1195 if (IS_ERR(gpio->clk)) { in aspeed_gpio_probe()
1196 dev_warn(&pdev->dev, in aspeed_gpio_probe()
1198 gpio->clk = NULL; in aspeed_gpio_probe()
1201 gpio->config = gpio_id->data; in aspeed_gpio_probe()
1203 gpio->chip.parent = &pdev->dev; in aspeed_gpio_probe()
1204 err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio); in aspeed_gpio_probe()
1205 gpio->chip.ngpio = (u16) ngpio; in aspeed_gpio_probe()
1207 gpio->chip.ngpio = gpio->config->nr_gpios; in aspeed_gpio_probe()
1208 gpio->chip.direction_input = aspeed_gpio_dir_in; in aspeed_gpio_probe()
1209 gpio->chip.direction_output = aspeed_gpio_dir_out; in aspeed_gpio_probe()
1210 gpio->chip.get_direction = aspeed_gpio_get_direction; in aspeed_gpio_probe()
1211 gpio->chip.request = aspeed_gpio_request; in aspeed_gpio_probe()
1212 gpio->chip.free = aspeed_gpio_free; in aspeed_gpio_probe()
1213 gpio->chip.get = aspeed_gpio_get; in aspeed_gpio_probe()
1214 gpio->chip.set = aspeed_gpio_set; in aspeed_gpio_probe()
1215 gpio->chip.set_config = aspeed_gpio_set_config; in aspeed_gpio_probe()
1216 gpio->chip.label = dev_name(&pdev->dev); in aspeed_gpio_probe()
1217 gpio->chip.base = -1; in aspeed_gpio_probe()
1220 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); in aspeed_gpio_probe()
1221 gpio->dcache = devm_kcalloc(&pdev->dev, in aspeed_gpio_probe()
1223 if (!gpio->dcache) in aspeed_gpio_probe()
1224 return -ENOMEM; in aspeed_gpio_probe()
1231 const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i]; in aspeed_gpio_probe() local
1232 void __iomem *addr = bank_reg(gpio, bank, reg_rdata); in aspeed_gpio_probe()
1233 gpio->dcache[i] = ioread32(addr); in aspeed_gpio_probe()
1234 aspeed_gpio_change_cmd_source(gpio, bank, 0, GPIO_CMDSRC_ARM); in aspeed_gpio_probe()
1235 aspeed_gpio_change_cmd_source(gpio, bank, 1, GPIO_CMDSRC_ARM); in aspeed_gpio_probe()
1236 aspeed_gpio_change_cmd_source(gpio, bank, 2, GPIO_CMDSRC_ARM); in aspeed_gpio_probe()
1237 aspeed_gpio_change_cmd_source(gpio, bank, 3, GPIO_CMDSRC_ARM); in aspeed_gpio_probe()
1244 gpio->irq = irq; in aspeed_gpio_probe()
1245 girq = &gpio->chip.irq; in aspeed_gpio_probe()
1248 girq->parent_handler = aspeed_gpio_irq_handler; in aspeed_gpio_probe()
1249 girq->num_parents = 1; in aspeed_gpio_probe()
1250 girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), GFP_KERNEL); in aspeed_gpio_probe()
1251 if (!girq->parents) in aspeed_gpio_probe()
1252 return -ENOMEM; in aspeed_gpio_probe()
1253 girq->parents[0] = gpio->irq; in aspeed_gpio_probe()
1254 girq->default_type = IRQ_TYPE_NONE; in aspeed_gpio_probe()
1255 girq->handler = handle_bad_irq; in aspeed_gpio_probe()
1256 girq->init_valid_mask = aspeed_init_irq_valid_mask; in aspeed_gpio_probe()
1258 gpio->offset_timer = in aspeed_gpio_probe()
1259 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL); in aspeed_gpio_probe()
1260 if (!gpio->offset_timer) in aspeed_gpio_probe()
1261 return -ENOMEM; in aspeed_gpio_probe()
1263 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); in aspeed_gpio_probe()