1 // SPDX-License-Identifier: GPL-2.0
3  * KUnit test for the FPGA Manager
12 #include <linux/fpga/fpga-mgr.h>
42 	struct fpga_manager *mgr;  member
48  * init_test_buffer() - Allocate and initialize a test image in a buffer.
64 	memset(buf + HEADER_SIZE, IMAGE_FILL, count - HEADER_SIZE);  in init_test_buffer()
71  * since, in this case, it is a failure of the FPGA manager itself, not this
74 static int op_parse_header(struct fpga_manager *mgr, struct fpga_image_info *info,  in op_parse_header()  argument
77 	struct mgr_stats *stats = mgr->priv;  in op_parse_header()
80 	stats->op_parse_header_state = mgr->state;  in op_parse_header()
81 	stats->op_parse_header_seq = stats->seq_num++;  in op_parse_header()
84 	info->header_size = HEADER_SIZE;  in op_parse_header()
85 	info->data_size = info->count - HEADER_SIZE;  in op_parse_header()
87 	stats->header_match = true;  in op_parse_header()
88 	for (i = 0; i < info->header_size; i++) {  in op_parse_header()
90 			stats->header_match = false;  in op_parse_header()
98 static int op_write_init(struct fpga_manager *mgr, struct fpga_image_info *info,  in op_write_init()  argument
101 	struct mgr_stats *stats = mgr->priv;  in op_write_init()
103 	stats->op_write_init_state = mgr->state;  in op_write_init()
104 	stats->op_write_init_seq = stats->seq_num++;  in op_write_init()
113 static int op_write(struct fpga_manager *mgr, const char *buf, size_t count)  in op_write()  argument
115 	struct mgr_stats *stats = mgr->priv;  in op_write()
118 	stats->op_write_state = mgr->state;  in op_write()
119 	stats->op_write_seq = stats->seq_num++;  in op_write()
121 	stats->image_match = true;  in op_write()
124 			stats->image_match = false;  in op_write()
137 static int op_write_sg(struct fpga_manager *mgr, struct sg_table *sgt)  in op_write_sg()  argument
139 	struct mgr_stats *stats = mgr->priv;  in op_write_sg()
144 	stats->op_write_sg_state = mgr->state;  in op_write_sg()
145 	stats->op_write_sg_seq = stats->seq_num++;  in op_write_sg()
147 	stats->image_match = true;  in op_write_sg()
148 	sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);  in op_write_sg()
151 		stats->image_match = false;  in op_write_sg()
159 				stats->image_match = false;  in op_write_sg()
169 static int op_write_complete(struct fpga_manager *mgr, struct fpga_image_info *info)  in op_write_complete()  argument
171 	struct mgr_stats *stats = mgr->priv;  in op_write_complete()
173 	stats->op_write_complete_state = mgr->state;  in op_write_complete()
174 	stats->op_write_complete_seq = stats->seq_num++;  in op_write_complete()
180  * Fake FPGA manager that implements all ops required to check the programming
194 	struct mgr_ctx *ctx = test->priv;  in fpga_mgr_test_get()
195 	struct fpga_manager *mgr;  in fpga_mgr_test_get()  local
197 	mgr = fpga_mgr_get(&ctx->pdev->dev);  in fpga_mgr_test_get()
198 	KUNIT_EXPECT_PTR_EQ(test, mgr, ctx->mgr);  in fpga_mgr_test_get()
200 	fpga_mgr_put(ctx->mgr);  in fpga_mgr_test_get()
205 	struct mgr_ctx *ctx = test->priv;  in fpga_mgr_test_lock()
208 	ret = fpga_mgr_lock(ctx->mgr);  in fpga_mgr_test_lock()
211 	ret = fpga_mgr_lock(ctx->mgr);  in fpga_mgr_test_lock()
212 	KUNIT_EXPECT_EQ(test, ret, -EBUSY);  in fpga_mgr_test_lock()
214 	fpga_mgr_unlock(ctx->mgr);  in fpga_mgr_test_lock()
220 	struct mgr_ctx *ctx = test->priv;  in fpga_mgr_test_img_load_buf()
226 	ctx->img_info->count = IMAGE_SIZE;  in fpga_mgr_test_img_load_buf()
227 	ctx->img_info->buf = img_buf;  in fpga_mgr_test_img_load_buf()
229 	ret = fpga_mgr_load(ctx->mgr, ctx->img_info);  in fpga_mgr_test_img_load_buf()
232 	KUNIT_EXPECT_TRUE(test, ctx->stats.header_match);  in fpga_mgr_test_img_load_buf()
233 	KUNIT_EXPECT_TRUE(test, ctx->stats.image_match);  in fpga_mgr_test_img_load_buf()
235 	KUNIT_EXPECT_EQ(test, ctx->stats.op_parse_header_state, FPGA_MGR_STATE_PARSE_HEADER);  in fpga_mgr_test_img_load_buf()
236 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_state, FPGA_MGR_STATE_WRITE_INIT);  in fpga_mgr_test_img_load_buf()
237 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_state, FPGA_MGR_STATE_WRITE);  in fpga_mgr_test_img_load_buf()
238 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_state, FPGA_MGR_STATE_WRITE_COMPLETE);  in fpga_mgr_test_img_load_buf()
240 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_seq, ctx->stats.op_parse_header_seq + 1);  in fpga_mgr_test_img_load_buf()
241 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_seq, ctx->stats.op_parse_header_seq + 2);  in fpga_mgr_test_img_load_buf()
242 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_seq, ctx->stats.op_parse_header_seq + 3);  in fpga_mgr_test_img_load_buf()
248 	struct mgr_ctx *ctx = test->priv;  in fpga_mgr_test_img_load_sgt()
258 	sg_init_one(sgt->sgl, img_buf, IMAGE_SIZE);  in fpga_mgr_test_img_load_sgt()
260 	ctx->img_info->sgt = sgt;  in fpga_mgr_test_img_load_sgt()
262 	ret = fpga_mgr_load(ctx->mgr, ctx->img_info);  in fpga_mgr_test_img_load_sgt()
265 	KUNIT_EXPECT_TRUE(test, ctx->stats.header_match);  in fpga_mgr_test_img_load_sgt()
266 	KUNIT_EXPECT_TRUE(test, ctx->stats.image_match);  in fpga_mgr_test_img_load_sgt()
268 	KUNIT_EXPECT_EQ(test, ctx->stats.op_parse_header_state, FPGA_MGR_STATE_PARSE_HEADER);  in fpga_mgr_test_img_load_sgt()
269 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_state, FPGA_MGR_STATE_WRITE_INIT);  in fpga_mgr_test_img_load_sgt()
270 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_sg_state, FPGA_MGR_STATE_WRITE);  in fpga_mgr_test_img_load_sgt()
271 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_state, FPGA_MGR_STATE_WRITE_COMPLETE);  in fpga_mgr_test_img_load_sgt()
273 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_seq, ctx->stats.op_parse_header_seq + 1);  in fpga_mgr_test_img_load_sgt()
274 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_sg_seq, ctx->stats.op_parse_header_seq + 2);  in fpga_mgr_test_img_load_sgt()
275 	KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_seq, ctx->stats.op_parse_header_seq + 3);  in fpga_mgr_test_img_load_sgt()
277 	sg_free_table(ctx->img_info->sgt);  in fpga_mgr_test_img_load_sgt()
287 	ctx->pdev = platform_device_register_simple("mgr_pdev", PLATFORM_DEVID_AUTO, NULL, 0);  in fpga_mgr_test_init()
288 	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->pdev);  in fpga_mgr_test_init()
290 	ctx->mgr = devm_fpga_mgr_register(&ctx->pdev->dev, "Fake FPGA Manager", &fake_mgr_ops,  in fpga_mgr_test_init()
291 					  &ctx->stats);  in fpga_mgr_test_init()
292 	KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->mgr));  in fpga_mgr_test_init()
294 	ctx->img_info = fpga_image_info_alloc(&ctx->pdev->dev);  in fpga_mgr_test_init()
295 	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->img_info);  in fpga_mgr_test_init()
297 	test->priv = ctx;  in fpga_mgr_test_init()
304 	struct mgr_ctx *ctx = test->priv;  in fpga_mgr_test_exit()
306 	fpga_image_info_free(ctx->img_info);  in fpga_mgr_test_exit()
307 	platform_device_unregister(ctx->pdev);  in fpga_mgr_test_exit()