1 // SPDX-License-Identifier: GPL-2.0
3  * FPGA Manager Driver for Altera SOCFPGA
5  *  Copyright (C) 2013-2015 Altera Corporation
9 #include <linux/fpga/fpga-mgr.h>
96 /* In power-up order. Reverse for power-down. */
98 	"FPGA-1.5V",
99 	"FPGA-1.1V",
100 	"FPGA-2.5V",
136 	return readl(priv->fpga_base_addr + reg_offset);  in socfpga_fpga_readl()
142 	writel(value, priv->fpga_base_addr + reg_offset);  in socfpga_fpga_writel()
148 	return __raw_readl(priv->fpga_base_addr + reg_offset);  in socfpga_fpga_raw_readl()
154 	__raw_writel(value, priv->fpga_base_addr + reg_offset);  in socfpga_fpga_raw_writel()
159 	writel(value, priv->fpga_data_addr);  in socfpga_fpga_data_writel()
230 	} while (timeout--);  in socfpga_fpga_dclk_set_and_wait_clear()
232 	return -ETIMEDOUT;  in socfpga_fpga_dclk_set_and_wait_clear()
248 	} while (timeout--);  in socfpga_fpga_wait_for_state()
250 	return -ETIMEDOUT;  in socfpga_fpga_wait_for_state()
296 		complete(&priv->status_complete);  in socfpga_fpga_isr()
307 	init_completion(&priv->status_complete);  in socfpga_fpga_wait_for_config_done()
311 						&priv->status_complete,  in socfpga_fpga_wait_for_config_done()
314 		ret = -ETIMEDOUT;  in socfpga_fpga_wait_for_config_done()
330 		return -EINVAL;  in socfpga_fpga_cfg_mode_get()
358 static int socfpga_fpga_reset(struct fpga_manager *mgr)  in socfpga_fpga_reset()  argument
360 	struct socfpga_fpga_priv *priv = mgr->priv;  in socfpga_fpga_reset()
366 	 *  - Set CTRL.CFGWDTH, CTRL.CDRATIO to match cfg mode  in socfpga_fpga_reset()
367 	 *  - Set CTRL.NCE to 0  in socfpga_fpga_reset()
377 	/* Step 3: Set CTRL.NCONFIGPULL to 1 to put FPGA in reset */  in socfpga_fpga_reset()
382 	/* Step 4: Wait for STATUS.MODE to report FPGA is in reset phase */  in socfpga_fpga_reset()
385 	/* Step 5: Set CONTROL.NCONFIGPULL to 0 to release FPGA from reset */  in socfpga_fpga_reset()
391 		return -ETIMEDOUT;  in socfpga_fpga_reset()
397  * Prepare the FPGA to receive the configuration data.
399 static int socfpga_fpga_ops_configure_init(struct fpga_manager *mgr,  in socfpga_fpga_ops_configure_init()  argument
403 	struct socfpga_fpga_priv *priv = mgr->priv;  in socfpga_fpga_ops_configure_init()
406 	if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {  in socfpga_fpga_ops_configure_init()
407 		dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");  in socfpga_fpga_ops_configure_init()
408 		return -EINVAL;  in socfpga_fpga_ops_configure_init()
410 	/* Steps 1 - 5: Reset the FPGA */  in socfpga_fpga_ops_configure_init()
411 	ret = socfpga_fpga_reset(mgr);  in socfpga_fpga_ops_configure_init()
415 	/* Step 6: Wait for FPGA to enter configuration phase */  in socfpga_fpga_ops_configure_init()
417 		return -ETIMEDOUT;  in socfpga_fpga_ops_configure_init()
431  * Step 9: write data to the FPGA data register
433 static int socfpga_fpga_ops_configure_write(struct fpga_manager *mgr,  in socfpga_fpga_ops_configure_write()  argument
436 	struct socfpga_fpga_priv *priv = mgr->priv;  in socfpga_fpga_ops_configure_write()
441 		return -EINVAL;  in socfpga_fpga_ops_configure_write()
443 	/* Write out the complete 32-bit chunks. */  in socfpga_fpga_ops_configure_write()
446 		count -= sizeof(u32);  in socfpga_fpga_ops_configure_write()
449 	/* Write out remaining non 32-bit chunks. */  in socfpga_fpga_ops_configure_write()
464 		return -EFAULT;  in socfpga_fpga_ops_configure_write()
470 static int socfpga_fpga_ops_configure_complete(struct fpga_manager *mgr,  in socfpga_fpga_ops_configure_complete()  argument
473 	struct socfpga_fpga_priv *priv = mgr->priv;  in socfpga_fpga_ops_configure_complete()
478 	 *  - Observe CONF_DONE and nSTATUS (active low)  in socfpga_fpga_ops_configure_complete()
479 	 *  - if CONF_DONE = 1 and nSTATUS = 1, configuration was successful  in socfpga_fpga_ops_configure_complete()
480 	 *  - if CONF_DONE = 0 and nSTATUS = 0, configuration failed  in socfpga_fpga_ops_configure_complete()
492 	 *  - Write 4 to DCLKCNT  in socfpga_fpga_ops_configure_complete()
493 	 *  - Wait for STATUS.DCNTDONE = 1  in socfpga_fpga_ops_configure_complete()
494 	 *  - Clear W1C bit in STATUS.DCNTDONE  in socfpga_fpga_ops_configure_complete()
497 		return -ETIMEDOUT;  in socfpga_fpga_ops_configure_complete()
501 		return -ETIMEDOUT;  in socfpga_fpga_ops_configure_complete()
510 /* Translate state register values to FPGA framework state */
520 static enum fpga_mgr_states socfpga_fpga_ops_state(struct fpga_manager *mgr)  in socfpga_fpga_ops_state()  argument
522 	struct socfpga_fpga_priv *priv = mgr->priv;  in socfpga_fpga_ops_state()
545 	struct device *dev = &pdev->dev;  in socfpga_fpga_probe()
547 	struct fpga_manager *mgr;  in socfpga_fpga_probe()  local
552 		return -ENOMEM;  in socfpga_fpga_probe()
554 	priv->fpga_base_addr = devm_platform_ioremap_resource(pdev, 0);  in socfpga_fpga_probe()
555 	if (IS_ERR(priv->fpga_base_addr))  in socfpga_fpga_probe()
556 		return PTR_ERR(priv->fpga_base_addr);  in socfpga_fpga_probe()
558 	priv->fpga_data_addr = devm_platform_ioremap_resource(pdev, 1);  in socfpga_fpga_probe()
559 	if (IS_ERR(priv->fpga_data_addr))  in socfpga_fpga_probe()
560 		return PTR_ERR(priv->fpga_data_addr);  in socfpga_fpga_probe()
562 	priv->irq = platform_get_irq(pdev, 0);  in socfpga_fpga_probe()
563 	if (priv->irq < 0)  in socfpga_fpga_probe()
564 		return priv->irq;  in socfpga_fpga_probe()
566 	ret = devm_request_irq(dev, priv->irq, socfpga_fpga_isr, 0,  in socfpga_fpga_probe()
571 	mgr = devm_fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager",  in socfpga_fpga_probe()
573 	return PTR_ERR_OR_ZERO(mgr);  in socfpga_fpga_probe()
578 	{ .compatible = "altr,socfpga-fpga-mgr", },
596 MODULE_DESCRIPTION("Altera SOCFPGA FPGA Manager");