54 	int ret = 0;  in decode_register()
74 #define L2C_CTL			0x87E080800000
75 #define L2C_CTL_DISIDXALIAS	BIT(0)
77 #define PCI_DEVICE_ID_THUNDER_LMC 0xa022
79 #define LMC_FADR		0x20
80 #define LMC_FADR_FDIMM(x)	((x >> 37) & 0x1)
81 #define LMC_FADR_FBUNK(x)	((x >> 36) & 0x1)
82 #define LMC_FADR_FBANK(x)	((x >> 32) & 0xf)
83 #define LMC_FADR_FROW(x)	((x >> 14) & 0xffff)
84 #define LMC_FADR_FCOL(x)	((x >> 0) & 0x1fff)
86 #define LMC_NXM_FADR		0x28
87 #define LMC_ECC_SYND		0x38
89 #define LMC_ECC_PARITY_TEST	0x108
91 #define LMC_INT_W1S		0x150
93 #define LMC_INT_ENA_W1C		0x158
94 #define LMC_INT_ENA_W1S		0x160
96 #define LMC_CONFIG		0x188
100 #define LMC_CONFIG_PBANK_LSB(x)	(((x) >> 5) & 0xF)
101 #define LMC_CONFIG_ROW_LSB(x)	(((x) >> 2) & 0x7)
103 #define LMC_CONTROL		0x190
106 #define LMC_INT			0x1F0
109 #define LMC_INT_DED_ERR		(0xFUL << 5)
110 #define LMC_INT_SEC_ERR         (0xFUL << 1)
111 #define LMC_INT_NXM_WR_MASK	BIT(0)
113 #define LMC_DDR_PLL_CTL		0x258
116 #define LMC_FADR_SCRAMBLED	0x330
144 	{0, 0, NULL},
152 #define LMC_INT_INTR_NXM_WR_ENA		BIT(0)
154 #define LMC_INT_ENA_ALL			GENMASK(5, 0)
156 #define LMC_DDR_PLL_CTL		0x258
159 #define LMC_CONTROL		0x190
160 #define LMC_CONTROL_RDIMM	BIT(0)
162 #define LMC_SCRAM_FADR		0x330
164 #define LMC_CHAR_MASK0		0x228
165 #define LMC_CHAR_MASK2		0x238
236 	snprintf(buf, count, "0x%016llx", pdata->_field);		    \
248 	res = kstrtoull_from_user(data, count, 0, &pdata->_field);	    \
265 	sprintf(buf, "0x%016llx", readq(pdata->regs + _reg));		    \
278 	res = kstrtoull_from_user(data, count, 0, &val);		    \
299  *	echo 0x802 > /sys/kernel/debug/<device number>/ecc_parity_test
311 	res = kstrtoull_from_user(data, count, 0, &val);  in thunderx_lmc_inject_int_write()
330 	snprintf(buf, sizeof(buf), "0x%016llx", lmc_int);  in thunderx_lmc_int_read()
334 #define TEST_PATTERN 0xa5
347 	cl_idx = (phys & 0x7f) >> 4;  in inject_ecc_fn()
359 	for (i = 0; i < lines; i++) {  in inject_ecc_fn()
367 		asm volatile("dc civac, %0\n"  in inject_ecc_fn()
372 	for (i = 0; i < lines; i++) {  in inject_ecc_fn()
378 		__asm__ volatile("sys #0,c11,C1,#2, %0\n"  in inject_ecc_fn()
382 	for (i = 0; i < lines; i++) {  in inject_ecc_fn()
388 		__asm__ volatile("sys #0,c11,C1,#1, %0"  in inject_ecc_fn()
392 	for (i = 0; i < lines; i++) {  in inject_ecc_fn()
398 		asm volatile("dc ivac, %0\n"  in inject_ecc_fn()
403 	return 0;  in inject_ecc_fn()
416 	atomic_set(&lmc->ecc_int, 0);  in thunderx_lmc_inject_ecc_write()
418 	lmc->mem = alloc_pages_node(lmc->node, GFP_KERNEL, 0);  in thunderx_lmc_inject_ecc_write()
424 		__free_pages(lmc->mem, 0);  in thunderx_lmc_inject_ecc_write()
433 		for (offs = 0; offs < PAGE_SIZE; offs += cline_size) {  in thunderx_lmc_inject_ecc_write()
444 	__free_pages(lmc->mem, 0);  in thunderx_lmc_inject_ecc_write()
475 		return 0;  in thunderx_create_debugfs_nodes()
480 	for (i = 0; i < num; i++) {  in thunderx_create_debugfs_nodes()
493 	phys_addr_t addr = 0;  in thunderx_faddr_to_phys()
522 	unsigned int number = 0;  in thunderx_get_num_lmcs()
553 	writeq(0, lmc->regs + LMC_CHAR_MASK0);  in thunderx_lmc_err_isr()
554 	writeq(0, lmc->regs + LMC_CHAR_MASK2);  in thunderx_lmc_err_isr()
555 	writeq(0x2, lmc->regs + LMC_ECC_PARITY_TEST);  in thunderx_lmc_err_isr()
627 					     0, -1, -1, -1, msg, other);  in thunderx_lmc_threaded_isr()
632 					     0, -1, -1, -1, msg, other);  in thunderx_lmc_threaded_isr()
648 	{ 0, },
656 	ret += max(node, 0) << 3;  in pci_dev_to_mc_idx()
682 	ret = pcim_iomap_regions(pdev, BIT(0), "thunderx_lmc");  in thunderx_lmc_probe()
698 	lmc->regs = pcim_iomap_table(pdev)[0];  in thunderx_lmc_probe()
723 	lmc->msix_ent.entry = 0;  in thunderx_lmc_probe()
725 	lmc->ring_head = 0;  in thunderx_lmc_probe()
726 	lmc->ring_tail = 0;  in thunderx_lmc_probe()
736 					thunderx_lmc_threaded_isr, 0,  in thunderx_lmc_probe()
743 	lmc->node = FIELD_GET(THUNDERX_NODE, pci_resource_start(pdev, 0));  in thunderx_lmc_probe()
749 	lmc->pbank_lsb = (lmc_config >> 5) & 0xf;  in thunderx_lmc_probe()
752 	lmc->rank_lsb -= FIELD_GET(LMC_CONFIG_RANK_ENA, lmc_config) ? 1 : 0;  in thunderx_lmc_probe()
790 				 ret, ret >= 0 ? " created" : "");  in thunderx_lmc_probe()
794 	return 0;  in thunderx_lmc_probe()
825 #define PCI_DEVICE_ID_THUNDER_OCX 0xa013
832 #define OCX_COM_INT		0x100
833 #define OCX_COM_INT_W1S		0x108
834 #define OCX_COM_INT_ENA_W1S	0x110
835 #define OCX_COM_INT_ENA_W1C	0x118
842 #define OCX_COM_RX_LANE			GENMASK(23, 0)
876 	{0, 0, NULL},
879 #define OCX_COM_LINKX_INT(x)		(0x120 + (x) * 8)
880 #define OCX_COM_LINKX_INT_W1S(x)	(0x140 + (x) * 8)
881 #define OCX_COM_LINKX_INT_ENA_W1S(x)	(0x160 + (x) * 8)
882 #define OCX_COM_LINKX_INT_ENA_W1C(x)	(0x180 + (x) * 8)
897 #define OCX_COM_LINK_REPLAY_SBE			BIT(0)
950 	{0, 0, NULL},
965 #define OCX_LNE_INT(x)			(0x8018 + (x) * 0x100)
966 #define OCX_LNE_INT_EN(x)		(0x8020 + (x) * 0x100)
967 #define OCX_LNE_BAD_CNT(x)		(0x8028 + (x) * 0x100)
968 #define OCX_LNE_CFG(x)			(0x8000 + (x) * 0x100)
969 #define OCX_LNE_STAT(x, y)		(0x8040 + (x) * 0x100 + (y) * 8)
974 #define OCX_LNE_CFG_RX_STAT_ENA			BIT(0)
983 #define OCX_LANE_SERDES_LOCK_LOSS		BIT(0)
985 #define OCX_COM_LANE_INT_UE       (0)
1030 	{0, 0, NULL},
1033 #define OCX_LNE_INT_ENA_ALL		(GENMASK(9, 8) | GENMASK(6, 0))
1034 #define OCX_COM_INT_ENA_ALL		(GENMASK(54, 50) | GENMASK(23, 0))
1036 					 GENMASK(9, 7) | GENMASK(5, 0))
1038 #define OCX_TLKX_ECC_CTL(x)		(0x10018 + (x) * 0x2000)
1039 #define OCX_RLKX_ECC_CTL(x)		(0x18018 + (x) * 0x2000)
1088 	for (lane = 0; lane < OCX_RX_LANES; lane++) {  in thunderx_ocx_com_isr()
1138 		for (lane = 0; lane < OCX_RX_LANES; lane++)  in thunderx_ocx_com_threaded_isr()
1154 			edac_device_handle_ce(ocx->edac_dev, 0, 0, msg);  in thunderx_ocx_com_threaded_isr()
1223 			edac_device_handle_ue(ocx->edac_dev, 0, 0, msg);  in thunderx_ocx_lnk_threaded_isr()
1225 			edac_device_handle_ce(ocx->edac_dev, 0, 0, msg);  in thunderx_ocx_lnk_threaded_isr()
1240 OCX_DEBUGFS_ATTR(tlk0_ecc_ctl, OCX_TLKX_ECC_CTL(0));
1244 OCX_DEBUGFS_ATTR(rlk0_ecc_ctl, OCX_RLKX_ECC_CTL(0));
1248 OCX_DEBUGFS_ATTR(com_link0_int, OCX_COM_LINKX_INT_W1S(0));
1252 OCX_DEBUGFS_ATTR(lne00_badcnt, OCX_LNE_BAD_CNT(0));
1324 	{ 0, },
1331 	for (lane = 0; lane < OCX_RX_LANES; lane++) {  in thunderx_ocx_clearstats()
1337 		for (stat = 0; stat < OCX_RX_LANE_STATS; stat++)  in thunderx_ocx_clearstats()
1359 	ret = pcim_iomap_regions(pdev, BIT(0), "thunderx_ocx");  in thunderx_ocx_probe()
1369 					      0, NULL, 0, idx);  in thunderx_ocx_probe()
1376 	ocx->com_ring_head = 0;  in thunderx_ocx_probe()
1377 	ocx->com_ring_tail = 0;  in thunderx_ocx_probe()
1378 	ocx->link_ring_head = 0;  in thunderx_ocx_probe()
1379 	ocx->link_ring_tail = 0;  in thunderx_ocx_probe()
1381 	ocx->regs = pcim_iomap_table(pdev)[0];  in thunderx_ocx_probe()
1390 	for (i = 0; i < OCX_INTS; i++) {  in thunderx_ocx_probe()
1392 		ocx->msix_ent[i].vector = 0;  in thunderx_ocx_probe()
1401 	for (i = 0; i < OCX_INTS; i++) {  in thunderx_ocx_probe()
1410 						0, "[EDAC] ThunderX OCX",  in thunderx_ocx_probe()
1436 				 ret, ret >= 0 ? " created" : "");  in thunderx_ocx_probe()
1444 	for (i = 0; i < OCX_RX_LANES; i++) {  in thunderx_ocx_probe()
1453 	for (i = 0; i < OCX_LINK_INTS; i++) {  in thunderx_ocx_probe()
1466 	return 0;  in thunderx_ocx_probe()
1481 	for (i = 0; i < OCX_INTS; i++) {  in thunderx_ocx_remove()
1503 #define PCI_DEVICE_ID_THUNDER_L2C_TAD 0xa02e
1504 #define PCI_DEVICE_ID_THUNDER_L2C_CBC 0xa02f
1505 #define PCI_DEVICE_ID_THUNDER_L2C_MCI 0xa030
1507 #define L2C_TAD_INT_W1C		0x40000
1508 #define L2C_TAD_INT_W1S		0x40008
1510 #define L2C_TAD_INT_ENA_W1C	0x40020
1511 #define L2C_TAD_INT_ENA_W1S	0x40028
1614 	{0, 0, NULL},
1630 #define L2C_TAD_TIMETWO		0x50000
1631 #define L2C_TAD_TIMEOUT		0x50100
1632 #define L2C_TAD_ERR		0x60000
1633 #define L2C_TAD_TQD_ERR		0x60100
1634 #define L2C_TAD_TTG_ERR		0x60200
1637 #define L2C_CBC_INT_W1C		0x60000
1639 #define L2C_CBC_INT_RSDSBE	 BIT(0)
1690 	{0, 0, NULL},
1693 #define L2C_CBC_INT_W1S		0x60008
1694 #define L2C_CBC_INT_ENA_W1C	0x60020
1699 #define L2C_CBC_INT_ENA_W1S	0x60028
1701 #define L2C_CBC_IODISOCIERR	0x80008
1702 #define L2C_CBC_IOCERR		0x80010
1703 #define L2C_CBC_RSDERR		0x80018
1704 #define L2C_CBC_MIBERR		0x80020
1707 #define L2C_MCI_INT_W1C		0x0
1709 #define L2C_MCI_INT_VBFSBE	 BIT(0)
1723 	{0, 0, NULL},
1726 #define L2C_MCI_INT_W1S		0x8
1727 #define L2C_MCI_INT_ENA_W1C	0x20
1731 #define L2C_MCI_INT_ENA_W1S	0x28
1733 #define L2C_MCI_ERR		0x10000
1902 			edac_device_handle_ue(l2c->edac_dev, 0, 0, msg);  in thunderx_l2c_threaded_isr()
1904 			edac_device_handle_ce(l2c->edac_dev, 0, 0, msg);  in thunderx_l2c_threaded_isr()
1942 	{ 0, },
1965 	ret = pcim_iomap_regions(pdev, BIT(0), "thunderx_l2c");  in thunderx_l2c_probe()
2007 					      name, 1, "L2C", 1, 0,  in thunderx_l2c_probe()
2008 					      NULL, 0, idx);  in thunderx_l2c_probe()
2017 	l2c->regs = pcim_iomap_table(pdev)[0];  in thunderx_l2c_probe()
2026 	l2c->ring_head = 0;  in thunderx_l2c_probe()
2027 	l2c->ring_tail = 0;  in thunderx_l2c_probe()
2029 	l2c->msix_ent.entry = 0;  in thunderx_l2c_probe()
2030 	l2c->msix_ent.vector = 0;  in thunderx_l2c_probe()
2041 					0, "[EDAC] ThunderX L2C",  in thunderx_l2c_probe()
2065 				 ret, ret >= 0 ? " created" : "");  in thunderx_l2c_probe()
2073 	return 0;  in thunderx_l2c_probe()
2115 	int rc = 0;  in thunderx_edac_init()