Lines Matching +full:bank +full:- +full:width
1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2012 - 2014 Xilinx, Inc.
141 /* DDR Control Register width definitions */
266 * struct ecc_error_info - ECC error log information.
269 * @bank: Bank number.
272 * @bankgrpnr: Bank group number.
278 u32 bank; member
286 * struct synps_ecc_status - ECC status information to report.
300 * struct synps_edac_priv - DDR memory controller private instance data.
310 * @bank_shift: Bit shifts for bank bit.
311 * @bankgrp_shift: Bit shifts for bank group bit.
332 * struct synps_platform_data - synps platform data structure.
348 * zynq_get_error_info - Get the current ECC error info.
359 base = priv->baseaddr; in zynq_get_error_info()
360 p = &priv->stat; in zynq_get_error_info()
366 p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT; in zynq_get_error_info()
367 p->ue_cnt = regval & STAT_UECNT_MASK; in zynq_get_error_info()
370 if (!(p->ce_cnt && (regval & LOG_VALID))) in zynq_get_error_info()
373 p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT; in zynq_get_error_info()
375 p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; in zynq_get_error_info()
376 p->ceinfo.col = regval & ADDR_COL_MASK; in zynq_get_error_info()
377 p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; in zynq_get_error_info()
378 p->ceinfo.data = readl(base + CE_DATA_31_0_OFST); in zynq_get_error_info()
379 edac_dbg(3, "CE bit position: %d data: %d\n", p->ceinfo.bitpos, in zynq_get_error_info()
380 p->ceinfo.data); in zynq_get_error_info()
385 if (!(p->ue_cnt && (regval & LOG_VALID))) in zynq_get_error_info()
389 p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; in zynq_get_error_info()
390 p->ueinfo.col = regval & ADDR_COL_MASK; in zynq_get_error_info()
391 p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; in zynq_get_error_info()
392 p->ueinfo.data = readl(base + UE_DATA_31_0_OFST); in zynq_get_error_info()
403 * zynqmp_get_error_info - Get the current ECC error info.
414 base = priv->baseaddr; in zynqmp_get_error_info()
415 p = &priv->stat; in zynqmp_get_error_info()
418 p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK; in zynqmp_get_error_info()
419 p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT; in zynqmp_get_error_info()
420 if (!p->ce_cnt) in zynqmp_get_error_info()
427 p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK); in zynqmp_get_error_info()
430 p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK); in zynqmp_get_error_info()
432 p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> in zynqmp_get_error_info()
434 p->ceinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >> in zynqmp_get_error_info()
436 p->ceinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); in zynqmp_get_error_info()
437 p->ceinfo.data = readl(base + ECC_CSYND0_OFST); in zynqmp_get_error_info()
442 if (!p->ue_cnt) in zynqmp_get_error_info()
446 p->ueinfo.row = (regval & ECC_CEADDR0_RW_MASK); in zynqmp_get_error_info()
448 p->ueinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >> in zynqmp_get_error_info()
450 p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> in zynqmp_get_error_info()
452 p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); in zynqmp_get_error_info()
453 p->ueinfo.data = readl(base + ECC_UESYND0_OFST); in zynqmp_get_error_info()
464 * handle_error - Handle Correctable and Uncorrectable errors.
472 struct synps_edac_priv *priv = mci->pvt_info; in handle_error()
475 if (p->ce_cnt) { in handle_error()
476 pinf = &p->ceinfo; in handle_error()
477 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in handle_error()
478 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
479 …"DDR ECC error type:%s Row %d Bank %d BankGroup Number %d Block Number %d Bit Position: %d Data: 0… in handle_error()
480 "CE", pinf->row, pinf->bank, in handle_error()
481 pinf->bankgrpnr, pinf->blknr, in handle_error()
482 pinf->bitpos, pinf->data); in handle_error()
484 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
485 "DDR ECC error type:%s Row %d Bank %d Col %d Bit Position: %d Data: 0x%08x", in handle_error()
486 "CE", pinf->row, pinf->bank, pinf->col, in handle_error()
487 pinf->bitpos, pinf->data); in handle_error()
491 p->ce_cnt, 0, 0, 0, 0, 0, -1, in handle_error()
492 priv->message, ""); in handle_error()
495 if (p->ue_cnt) { in handle_error()
496 pinf = &p->ueinfo; in handle_error()
497 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in handle_error()
498 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
499 "DDR ECC error type :%s Row %d Bank %d BankGroup Number %d Block Number %d", in handle_error()
500 "UE", pinf->row, pinf->bank, in handle_error()
501 pinf->bankgrpnr, pinf->blknr); in handle_error()
503 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
504 "DDR ECC error type :%s Row %d Bank %d Col %d ", in handle_error()
505 "UE", pinf->row, pinf->bank, pinf->col); in handle_error()
509 p->ue_cnt, 0, 0, 0, 0, 0, -1, in handle_error()
510 priv->message, ""); in handle_error()
519 if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR) in enable_intr()
521 priv->baseaddr + ECC_CLR_OFST); in enable_intr()
524 priv->baseaddr + DDR_QOS_IRQ_EN_OFST); in enable_intr()
531 if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR) in disable_intr()
532 writel(0x0, priv->baseaddr + ECC_CLR_OFST); in disable_intr()
535 priv->baseaddr + DDR_QOS_IRQ_DB_OFST); in disable_intr()
539 * intr_handler - Interrupt Handler for ECC interrupts.
552 priv = mci->pvt_info; in intr_handler()
553 p_data = priv->p_data; in intr_handler()
559 if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) { in intr_handler()
560 regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); in intr_handler()
566 status = p_data->get_error_info(priv); in intr_handler()
570 priv->ce_cnt += priv->stat.ce_cnt; in intr_handler()
571 priv->ue_cnt += priv->stat.ue_cnt; in intr_handler()
572 handle_error(mci, &priv->stat); in intr_handler()
575 priv->ce_cnt, priv->ue_cnt); in intr_handler()
577 if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) in intr_handler()
578 writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); in intr_handler()
586 * check_errors - Check controller for ECC errors.
597 priv = mci->pvt_info; in check_errors()
598 p_data = priv->p_data; in check_errors()
600 status = p_data->get_error_info(priv); in check_errors()
604 priv->ce_cnt += priv->stat.ce_cnt; in check_errors()
605 priv->ue_cnt += priv->stat.ue_cnt; in check_errors()
606 handle_error(mci, &priv->stat); in check_errors()
609 priv->ce_cnt, priv->ue_cnt); in check_errors()
613 * zynq_get_dtype - Return the controller memory width.
616 * Get the EDAC device type width appropriate for the current controller
619 * Return: a device type width enumeration.
624 u32 width; in zynq_get_dtype() local
626 width = readl(base + CTRL_OFST); in zynq_get_dtype()
627 width = (width & CTRL_BW_MASK) >> CTRL_BW_SHIFT; in zynq_get_dtype()
629 switch (width) { in zynq_get_dtype()
644 * zynqmp_get_dtype - Return the controller memory width.
647 * Get the EDAC device type width appropriate for the current controller
650 * Return: a device type width enumeration.
655 u32 width; in zynqmp_get_dtype() local
657 width = readl(base + CTRL_OFST); in zynqmp_get_dtype()
658 width = (width & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT; in zynqmp_get_dtype()
659 switch (width) { in zynqmp_get_dtype()
677 * zynq_get_ecc_state - Return the controller ECC enable/disable status.
701 * zynqmp_get_ecc_state - Return the controller ECC enable/disable status.
706 * Return: a ECC status boolean i.e true/false - enabled/disabled.
726 * get_memsize - Read the size of the attached memory device.
740 * zynq_get_mtype - Return the controller memory type.
764 * zynqmp_get_mtype - Returns controller memory type.
792 * init_csrows - Initialize the csrow data.
800 struct synps_edac_priv *priv = mci->pvt_info; in init_csrows()
807 p_data = priv->p_data; in init_csrows()
809 for (row = 0; row < mci->nr_csrows; row++) { in init_csrows()
810 csi = mci->csrows[row]; in init_csrows()
813 for (j = 0; j < csi->nr_channels; j++) { in init_csrows()
814 dimm = csi->channels[j]->dimm; in init_csrows()
815 dimm->edac_mode = EDAC_SECDED; in init_csrows()
816 dimm->mtype = p_data->get_mtype(priv->baseaddr); in init_csrows()
817 dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels; in init_csrows()
818 dimm->grain = SYNPS_EDAC_ERR_GRAIN; in init_csrows()
819 dimm->dtype = p_data->get_dtype(priv->baseaddr); in init_csrows()
825 * mc_init - Initialize one driver instance.
830 * related driver-private data associated with the memory controller the
837 mci->pdev = &pdev->dev; in mc_init()
838 priv = mci->pvt_info; in mc_init()
842 mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2; in mc_init()
843 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; in mc_init()
844 mci->scrub_cap = SCRUB_HW_SRC; in mc_init()
845 mci->scrub_mode = SCRUB_NONE; in mc_init()
847 mci->edac_cap = EDAC_FLAG_SECDED; in mc_init()
848 mci->ctl_name = "synps_ddr_controller"; in mc_init()
849 mci->dev_name = SYNPS_EDAC_MOD_STRING; in mc_init()
850 mci->mod_name = SYNPS_EDAC_MOD_VER; in mc_init()
852 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in mc_init()
856 mci->edac_check = check_errors; in mc_init()
859 mci->ctl_page_to_phys = NULL; in mc_init()
867 struct synps_edac_priv *priv = mci->pvt_info; in setup_irq()
877 ret = devm_request_irq(&pdev->dev, irq, intr_handler, in setup_irq()
878 0, dev_name(&pdev->dev), mci); in setup_irq()
924 .compatible = "xlnx,zynq-ddrc-a05",
928 .compatible = "xlnx,zynqmp-ddrc-2.40a",
932 .compatible = "snps,ddrc-3.80a",
946 * ddr_poison_setup - Update poison registers.
954 int col = 0, row = 0, bank = 0, bankgrp = 0, rank = 0, regval; in ddr_poison_setup() local
958 hif_addr = priv->poison_addr >> 3; in ddr_poison_setup()
961 if (priv->row_shift[index]) in ddr_poison_setup()
962 row |= (((hif_addr >> priv->row_shift[index]) & in ddr_poison_setup()
969 if (priv->col_shift[index] || index < 3) in ddr_poison_setup()
970 col |= (((hif_addr >> priv->col_shift[index]) & in ddr_poison_setup()
977 if (priv->bank_shift[index]) in ddr_poison_setup()
978 bank |= (((hif_addr >> priv->bank_shift[index]) & in ddr_poison_setup()
985 if (priv->bankgrp_shift[index]) in ddr_poison_setup()
986 bankgrp |= (((hif_addr >> priv->bankgrp_shift[index]) in ddr_poison_setup()
992 if (priv->rank_shift[0]) in ddr_poison_setup()
993 rank = (hif_addr >> priv->rank_shift[0]) & BIT(0); in ddr_poison_setup()
997 writel(regval, priv->baseaddr + ECC_POISON0_OFST); in ddr_poison_setup()
1000 regval |= (bank << ECC_POISON1_BANKNR_SHIFT) & ECC_POISON1_BANKNR_MASK; in ddr_poison_setup()
1002 writel(regval, priv->baseaddr + ECC_POISON1_OFST); in ddr_poison_setup()
1010 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_error_show()
1014 readl(priv->baseaddr + ECC_POISON0_OFST), in inject_data_error_show()
1015 readl(priv->baseaddr + ECC_POISON1_OFST), in inject_data_error_show()
1016 priv->poison_addr); in inject_data_error_show()
1024 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_error_store()
1026 if (kstrtoul(data, 0, &priv->poison_addr)) in inject_data_error_store()
1027 return -EINVAL; in inject_data_error_store()
1039 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_poison_show()
1042 (((readl(priv->baseaddr + ECC_CFG1_OFST)) & 0x3) == 0x3) in inject_data_poison_show()
1051 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_poison_store()
1053 writel(0, priv->baseaddr + DDRC_SWCTL); in inject_data_poison_store()
1055 writel(ECC_CEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST); in inject_data_poison_store()
1057 writel(ECC_UEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST); in inject_data_poison_store()
1058 writel(1, priv->baseaddr + DDRC_SWCTL); in inject_data_poison_store()
1070 rc = device_create_file(&mci->dev, &dev_attr_inject_data_error); in edac_create_sysfs_attributes()
1073 rc = device_create_file(&mci->dev, &dev_attr_inject_data_poison); in edac_create_sysfs_attributes()
1081 device_remove_file(&mci->dev, &dev_attr_inject_data_error); in edac_remove_sysfs_attributes()
1082 device_remove_file(&mci->dev, &dev_attr_inject_data_poison); in edac_remove_sysfs_attributes()
1090 priv->row_shift[0] = (addrmap[5] & ROW_MAX_VAL_MASK) + ROW_B0_BASE; in setup_row_address_map()
1091 priv->row_shift[1] = ((addrmap[5] >> 8) & in setup_row_address_map()
1097 priv->row_shift[index] = addrmap_row_b2_10 + in setup_row_address_map()
1101 priv->row_shift[2] = (addrmap[9] & in setup_row_address_map()
1103 priv->row_shift[3] = ((addrmap[9] >> 8) & in setup_row_address_map()
1105 priv->row_shift[4] = ((addrmap[9] >> 16) & in setup_row_address_map()
1107 priv->row_shift[5] = ((addrmap[9] >> 24) & in setup_row_address_map()
1109 priv->row_shift[6] = (addrmap[10] & in setup_row_address_map()
1111 priv->row_shift[7] = ((addrmap[10] >> 8) & in setup_row_address_map()
1113 priv->row_shift[8] = ((addrmap[10] >> 16) & in setup_row_address_map()
1115 priv->row_shift[9] = ((addrmap[10] >> 24) & in setup_row_address_map()
1117 priv->row_shift[10] = (addrmap[11] & in setup_row_address_map()
1121 priv->row_shift[11] = (((addrmap[5] >> 24) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1124 priv->row_shift[12] = ((addrmap[6] & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1127 priv->row_shift[13] = (((addrmap[6] >> 8) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1130 priv->row_shift[14] = (((addrmap[6] >> 16) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1133 priv->row_shift[15] = (((addrmap[6] >> 24) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1136 priv->row_shift[16] = ((addrmap[7] & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1139 priv->row_shift[17] = (((addrmap[7] >> 8) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1146 u32 width, memtype; in setup_column_address_map() local
1149 memtype = readl(priv->baseaddr + CTRL_OFST); in setup_column_address_map()
1150 width = (memtype & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT; in setup_column_address_map()
1152 priv->col_shift[0] = 0; in setup_column_address_map()
1153 priv->col_shift[1] = 1; in setup_column_address_map()
1154 priv->col_shift[2] = (addrmap[2] & COL_MAX_VAL_MASK) + COL_B2_BASE; in setup_column_address_map()
1155 priv->col_shift[3] = ((addrmap[2] >> 8) & in setup_column_address_map()
1157 priv->col_shift[4] = (((addrmap[2] >> 16) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1160 priv->col_shift[5] = (((addrmap[2] >> 24) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1163 priv->col_shift[6] = ((addrmap[3] & COL_MAX_VAL_MASK) == in setup_column_address_map()
1166 priv->col_shift[7] = (((addrmap[3] >> 8) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1169 priv->col_shift[8] = (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1172 priv->col_shift[9] = (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1175 if (width == DDRCTL_EWDTH_64) { in setup_column_address_map()
1177 priv->col_shift[10] = ((addrmap[4] & in setup_column_address_map()
1181 priv->col_shift[11] = (((addrmap[4] >> 8) & in setup_column_address_map()
1186 priv->col_shift[11] = ((addrmap[4] & in setup_column_address_map()
1190 priv->col_shift[13] = (((addrmap[4] >> 8) & in setup_column_address_map()
1195 } else if (width == DDRCTL_EWDTH_32) { in setup_column_address_map()
1197 priv->col_shift[10] = (((addrmap[3] >> 24) & in setup_column_address_map()
1201 priv->col_shift[11] = ((addrmap[4] & in setup_column_address_map()
1206 priv->col_shift[11] = (((addrmap[3] >> 24) & in setup_column_address_map()
1210 priv->col_shift[13] = ((addrmap[4] & in setup_column_address_map()
1217 priv->col_shift[10] = (((addrmap[3] >> 16) & in setup_column_address_map()
1221 priv->col_shift[11] = (((addrmap[3] >> 24) & in setup_column_address_map()
1225 priv->col_shift[13] = ((addrmap[4] & in setup_column_address_map()
1230 priv->col_shift[11] = (((addrmap[3] >> 16) & in setup_column_address_map()
1234 priv->col_shift[13] = (((addrmap[3] >> 24) & in setup_column_address_map()
1241 if (width) { in setup_column_address_map()
1242 for (index = 9; index > width; index--) { in setup_column_address_map()
1243 priv->col_shift[index] = priv->col_shift[index - width]; in setup_column_address_map()
1244 priv->col_shift[index - width] = 0; in setup_column_address_map()
1252 priv->bank_shift[0] = (addrmap[1] & BANK_MAX_VAL_MASK) + BANK_B0_BASE; in setup_bank_address_map()
1253 priv->bank_shift[1] = ((addrmap[1] >> 8) & in setup_bank_address_map()
1255 priv->bank_shift[2] = (((addrmap[1] >> 16) & in setup_bank_address_map()
1264 priv->bankgrp_shift[0] = (addrmap[8] & in setup_bg_address_map()
1266 priv->bankgrp_shift[1] = (((addrmap[8] >> 8) & BANKGRP_MAX_VAL_MASK) == in setup_bg_address_map()
1274 priv->rank_shift[0] = ((addrmap[0] & RANK_MAX_VAL_MASK) == in setup_rank_address_map()
1280 * setup_address_map - Set Address Map by querying ADDRMAP registers.
1296 addrmap[index] = readl(priv->baseaddr + addrmap_offset); in setup_address_map()
1312 * mc_probe - Check controller and bind driver.
1331 baseaddr = devm_ioremap_resource(&pdev->dev, res); in mc_probe()
1335 p_data = of_device_get_match_data(&pdev->dev); in mc_probe()
1337 return -ENODEV; in mc_probe()
1339 if (!p_data->get_ecc_state(baseaddr)) { in mc_probe()
1341 return -ENXIO; in mc_probe()
1356 return -ENOMEM; in mc_probe()
1359 priv = mci->pvt_info; in mc_probe()
1360 priv->baseaddr = baseaddr; in mc_probe()
1361 priv->p_data = p_data; in mc_probe()
1365 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in mc_probe()
1379 if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) { in mc_probe()
1388 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) in mc_probe()
1396 if (!(priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)) in mc_probe()
1408 * mc_remove - Unbind driver from controller.
1416 struct synps_edac_priv *priv = mci->pvt_info; in mc_remove()
1418 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) in mc_remove()
1422 if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) in mc_remove()
1426 edac_mc_del_mc(&pdev->dev); in mc_remove()
1432 .name = "synopsys-edac",