drivers/edac/ppc4xx_edac.c

35  *       - 4-bit SEC/DED
53  *   - Up to 4 GiB per bank/rank in 64-bit mode and up to 2 GiB
66  *   - Four (4) memory banks/ranks.
81  * the other known ECC-capable controllers prevalent in other 4xx
84  *   - IBM SDRAM (405GP, 405CR and 405EP) "ibm,sdram-4xx"
85  *   - IBM DDR1 (440GP, 440GX, 440EP and 440GR) "ibm,sdram-4xx-ddr"
86  *   - Denali DDR1/DDR2 (440EPX and 440GRX) "denali,sdram-4xx-ddr2"
132 #define SDRAM_MBCF_SZ_MiB_MIN		4
140  * The ibm,sdram-4xx-ddr2 Device Control Registers (DCRs) are
189 		.compatible	= "ibm,sdram-4xx-ddr2"
644  * status registers that deal with ibm,sdram-4xx-ddr2 ECC errors.
672  * ibm,sdram-4xx-ddr2 ECC errors.
695  * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
726  * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
752  *       associated with the ibm,sdram-4xx-ddr2 controller being
790  * (CE) and uncorrectable (UE) ECC errors for the ibm,sdram-4xx-ddr2
863  *       associated with the ibm,sdram-4xx-ddr2 controller for which
870  * with the EDAC memory controller instance. An ibm,sdram-4xx-ddr2
956 		 * page size (PAGE_SIZE) or the memory width (2 or 4).  in ppc4xx_edac_init_csrows()
989  * ibm,sdram-4xx-ddr2 memory controller the instance is bound to.
1072  *       associated with the ibm,sdram-4xx-ddr2 controller for which
1203  * This routine probes a specific ibm,sdram-4xx-ddr2 controller
1327  * with the specified ibm,sdram-4xx-ddr2 controller described by the