Lines Matching +full:ddr +full:- +full:config
6 config EDAC_ATOMIC_SCRUB
9 config EDAC_SUPPORT
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
26 config EDAC_LEGACY_SYSFS
34 config EDAC_DEBUG
40 levels are 0-4 (from low to high) and by default it is set to 2.
43 config EDAC_DECODE_MCE
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
55 config EDAC_GHES
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
65 When this option is enabled, it will disable the hardware-driven
69 It should be noticed that keeping both GHES and a hardware-driven
78 config EDAC_AMD64
96 - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 - inject_word (0..8, 16-bit word of 16-byte section),
98 - inject_ecc_vector (hex ecc vector: select bits of inject word)
103 config EDAC_AL_MC
110 config EDAC_AMD76X
117 config EDAC_E7XXX
124 config EDAC_E752X
131 config EDAC_I82443BXGX
139 config EDAC_I82875P
146 config EDAC_I82975X
153 config EDAC_I3000
160 config EDAC_I3200
167 config EDAC_IE31200
172 E3-1200 based DRAM controllers.
174 config EDAC_X38
181 config EDAC_I5400
188 config EDAC_I7CORE
197 config EDAC_I82860
204 config EDAC_R82600
211 config EDAC_I5000
219 config EDAC_I5100
226 config EDAC_I7300
233 config EDAC_SBRIDGE
234 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
240 config EDAC_SKX
249 system has non-volatile DIMMs you should also manually
252 config EDAC_I10NM
261 system has non-volatile DIMMs you should also manually
264 config EDAC_PND2
272 micro-server but may appear on others in the future.
274 config EDAC_IGEN6
280 client SoC Integrated Memory Controller using In-Band ECC IP.
281 This In-Band ECC is first used on the Elkhart Lake SoC but
284 config EDAC_MPC85XX
291 config EDAC_LAYERSCAPE
292 tristate "Freescale Layerscape DDR"
298 config EDAC_PASEMI
305 config EDAC_CELL
313 config EDAC_PPC4XX
322 config EDAC_AMD8131
323 tristate "AMD8131 HyperTransport PCI-X Tunnel"
327 AMD8131 HyperTransport PCI-X Tunnel chip.
331 config EDAC_AMD8111
340 config EDAC_CPC925
349 config EDAC_HIGHBANK_MC
356 config EDAC_HIGHBANK_L2
363 config EDAC_OCTEON_PC
370 config EDAC_OCTEON_L2C
377 config EDAC_OCTEON_LMC
384 config EDAC_OCTEON_PCI
391 config EDAC_THUNDERX
401 config EDAC_ALTERA
409 config EDAC_ALTERA_SDRAM
418 config EDAC_ALTERA_L2C
426 config EDAC_ALTERA_OCRAM
427 bool "Altera On-Chip RAM ECC"
431 Altera On-Chip RAM Memory for Altera SoCs.
433 config EDAC_ALTERA_ETHERNET
440 config EDAC_ALTERA_NAND
447 config EDAC_ALTERA_DMA
454 config EDAC_ALTERA_USB
461 config EDAC_ALTERA_QSPI
468 config EDAC_ALTERA_SDMMC
475 config EDAC_SIFIVE
481 config EDAC_ARMADA_XP
482 bool "Marvell Armada XP DDR and L2 Cache ECC"
486 DDR RAM and L2 cache controllers.
488 config EDAC_SYNOPSYS
489 tristate "Synopsys DDR Memory Controller"
492 Support for error detection and correction on the Synopsys DDR
495 config EDAC_XGENE
496 tristate "APM X-Gene SoC"
500 APM X-Gene family of SOCs.
502 config EDAC_TI
508 config EDAC_QCOM
522 config EDAC_ASPEED
531 config EDAC_BLUEFIELD
538 config EDAC_DMC520
539 tristate "ARM DMC-520 ECC"
543 SoCs with ARM DMC-520 DRAM controller.
545 config EDAC_ZYNQMP
553 config EDAC_NPCM
554 tristate "Nuvoton NPCM DDR Memory Controller"
557 Support for error detection and correction on the Nuvoton NPCM DDR
561 error detection (in-line ECC in which a section 1/8th of the memory
564 config EDAC_VERSAL
565 tristate "Xilinx Versal DDR Memory Controller"
568 Support for error detection and correction on the Xilinx Versal DDR