Kconfig - OpenGrok cross reference for /linux-6.8/drivers/edac/Kconfig

16 	  EDAC is a subsystem along with hardware-specific drivers designed to
17 	  report hardware errors. These are low-level errors that are reported
22 	  The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 	  levels are 0-4 (from low to high) and by default it is set to 2.
44 	tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 	  occurring on your machine in human-readable form.
60 	  Not all machines support hardware-driven error report. Some of those
61 	  provide a BIOS-driven error report mechanism via ACPI, using the
65 	  When this option is enabled, it will disable the hardware-driven
69 	  It should be noticed that keeping both GHES and a hardware-driven
93 	  When enabled, in each of the respective memory controller directories
96 	  - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 	  - inject_word (0..8, 16-bit word of 16-byte section),
98 	  - inject_ecc_vector (hex ecc vector: select bits of inject word)
104 	tristate "Amazon's Annapurna Lab Memory Controller"
172 	  E3-1200 based DRAM controllers.
193 	  i7 Core (Nehalem) Integrated Memory Controller that exists on
234 	tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
249 	  system has non-volatile DIMMs you should also manually
261 	  system has non-volatile DIMMs you should also manually
270 	  Pondicherry2 Integrated Memory Controller. This SoC IP is
272 	  micro-server but may appear on others in the future.
280 	  client SoC Integrated Memory Controller using In-Band ECC IP.
281 	  This In-Band ECC is first used on the Elkhart Lake SoC but
306 	tristate "Cell Broadband Engine memory controller"
310 	  Cell Broadband Engine internal memory controller
314 	tristate "PPC4xx IBM DDR2 Memory Controller"
318 	  with the IBM DDR2 memory controller found in various
323 	tristate "AMD8131 HyperTransport PCI-X Tunnel"
327 	  AMD8131 HyperTransport PCI-X Tunnel chip.
341 	tristate "IBM CPC925 Memory Controller (PPC970FX)"
345 	  IBM CPC925 Bridge and Memory Controller, which is
350 	tristate "Highbank Memory Controller"
354 	  Calxeda Highbank memory controller.
361 	  Calxeda Highbank memory controller.
378 	tristate "Cavium Octeon DRAM Memory Controller (LMC)"
385 	tristate "Cavium Octeon PCI Controller"
410 	bool "Altera SDRAM ECC"
414 	  Altera SDRAM Memory for Altera SoCs. Note that the
415 	  preloader must initialize the SDRAM before loading
427 	bool "Altera On-Chip RAM ECC"
431 	  Altera On-Chip RAM Memory for Altera SoCs.
482 	bool "Marvell Armada XP DDR and L2 Cache ECC"
485 	  Support for error correction and detection on the Marvell Aramada XP
489 	tristate "Synopsys DDR Memory Controller"
493 	  memory controller.
496 	tristate "APM X-Gene SoC"
500 	  APM X-Gene family of SOCs.
503 	tristate "Texas Instruments DDR3 ECC Controller"
509 	tristate "QCOM EDAC Controller"
516 	  As of now, it supports error reporting for Last Level Cache Controller (LLCC)
539 	tristate "ARM DMC-520 ECC"
543 	  SoCs with ARM DMC-520 DRAM controller.
546 	tristate "Xilinx ZynqMP OCM Controller"
550 	  Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be
554 	tristate "Nuvoton NPCM DDR Memory Controller"
558 	  memory controller.
560 	  The memory controller supports single bit error correction, double bit
561 	  error detection (in-line ECC in which a section 1/8th of the memory
565 	tristate "Xilinx Versal DDR Memory Controller"
569 	  memory controller.