1 /* SPDX-License-Identifier: GPL-2.0 */
45 	u64 bits;  member
51 		u64 total_wq_size:16;
65 	u64 bits;  member
79 	u64 bits;  member
88 	u64 bits;  member
97 	u64 bits[4];  member
107 		u64 grpcfg:16;
108 		u64 wqcfg:16;
109 		u64 msix_perm:16;
110 		u64 ims:16;
111 		u64 perfmon:16;
114 	u64 bits[2];  member
128 	u32 bits;  member
139 	u32 bits;  member
149 	u32 bits;  member
183 	u32 bits;  member
213 	u32 bits;  member
276 		u64 batch_idx:16;
277 		u64 rsvd4:16;
284 	u64 bits[4];  member
303 	u64 bits;  member
316 		u64 size:16;
320 	u64 bits[2];  member
334 	u32 bits;  member
352 	u64 bits;  member
363 		/* bytes 0-3 */
367 		/* bytes 4-7 */
371 		/* bytes 8-11 */
382 		/* bytes 12-15 */
387 		/* bytes 16-19 */
392 		/* bytes 20-23 */
397 		/* bytes 24-27 */
404 		/* bytes 28-31 */
407 		/* bytes 32-63 */
410 	u32 bits[16];  member
421  * idxd - struct idxd *
422  * n - wq id
423  * ofs - the index of the 32b dword for the config register
427  * Each register is 32bits. The ofs gives us the number of register to access.
432 	(__idxd_dev)->wqcfg_offset + (n) * (__idxd_dev)->wqcfg_size + sizeof(u32) * (ofs);	\
435 #define WQCFG_STRIDES(_idxd_dev) ((_idxd_dev)->wqcfg_size / sizeof(u32))
442  * idxd - struct idxd *
443  * n - group id
444  * ofs - the index of the 64b qword for the config register
446  * The GRPCFG register block is divided into three sub-registers, which
448  * to the register block that contains the three sub-registers.
449  * Each register block is 64bits. And the ofs gives us the offset
452 #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\
454 #define GRPENGCFG_OFFSET(idxd_dev, n) ((idxd_dev)->grpcfg_offset + (n) * GRPCFG_SIZE + 32)
455 #define GRPFLGCFG_OFFSET(idxd_dev, n) ((idxd_dev)->grpcfg_offset + (n) * GRPCFG_SIZE + 40)
465 		u64 global_event_category:16;
474 	u64 bits;  member
483 	u64 bits;  member
569 		u32 head:16;
570 		u32 rsvd:16;
571 		u32 tail:16;
580 	u64 bits;  member