Lines Matching +full:port +full:- +full:mapping +full:- +full:mode
1 /* SPDX-License-Identifier: GPL-2.0-only */
19 * (port-driver, region-driver, nvdimm object-drivers... etc).
81 return -EINVAL; in eig_to_granularity()
86 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */
94 *ways = 3 << (eiw - 8); in eiw_to_ways()
97 return -EINVAL; in eiw_to_ways()
107 return -EINVAL; in granularity_to_eig()
108 *eig = ilog2(granularity) - 8; in granularity_to_eig()
115 return -EINVAL; in ways_to_eiw()
121 return -EINVAL; in ways_to_eiw()
124 return -EINVAL; in ways_to_eiw()
173 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */
199 * Using struct_group() allows for per register-block-type helper routines,
200 * without requiring block-type agnostic code to include the prefix.
227 * RCH downstream port specific RAS register
228 * @aer: CXL 3.0 8.2.1.1 RCH Downstream Port RCRB
258 * struct cxl_register_map - DVSEC harvested register block mapping parameters
260 * @base: virtual base of the register-block-BAR + @block_offset
262 * @max_size: maximum mapping size to perform register search
303 #define CXL_RESOURCE_NONE ((resource_size_t) -1)
332 #define CXL_QOS_CLASS_INVALID -1
335 * struct cxl_decoder - Common CXL HDM Decoder Attributes
344 * @commit: device/decoder-type specific callback to commit settings to hw
345 * @reset: device/decoder-type specific callback to reset hw settings
372 static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode) in cxl_decoder_mode_name() argument
381 if (mode >= CXL_DECODER_NONE && mode <= CXL_DECODER_MIXED) in cxl_decoder_mode_name()
382 return names[mode]; in cxl_decoder_mode_name()
396 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder
400 * @mode: which memory type / access-mode-partition this decoder targets
408 enum cxl_decoder_mode mode; member
414 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder
421 * come in two flavors, root-level decoders, statically defined by platform
422 * firmware, and mid-level decoders, where interleave-granularity,
423 * interleave-width, and the target list are mutable.
436 * struct cxl_root_decoder - Static platform CXL address decoder
456 * enum cxl_config_state - State machine for region configuration
463 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware
474 * struct cxl_region_params - region settings
511 * struct cxl_region - CXL region
514 * @mode: Endpoint decoder allocation / access mode
524 enum cxl_decoder_mode mode; member
535 struct cxl_port *port; member
562 struct cxl_pmem_region_mapping mapping[]; member
572 * struct cxl_port - logical collection of upstream port devices and
573 * downstream port devices to construct a CXL memory
575 * @dev: this port's device
576 * @uport_dev: PCI or platform device implementing the upstream port capability
577 * @host_bridge: Shortcut to the platform attach point for this port
578 * @id: id for port device-name
580 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port
581 * @regions: cxl_region_ref instances, regions mapped by this port
582 * @parent_dport: dport that points to this port in the parent
584 * @reg_map: component and ras register mapping parameters
588 * @dead: last ep has been removed, force port re-creation
589 * @depth: How deep this port is relative to the root. depth 0 is the root.
619 * struct cxl_root - logical collection of root cxl_port items
621 * @port: cxl_port member
625 struct cxl_port port; member
630 to_cxl_root(const struct cxl_port *port) in to_cxl_root() argument
632 return container_of(port, struct cxl_root, port); in to_cxl_root()
642 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev) in cxl_find_dport_by_dev() argument
644 return xa_load(&port->dports, (unsigned long)dport_dev); in cxl_find_dport_by_dev()
653 * struct cxl_dport - CXL downstream port
655 * @reg_map: component and ras register mapping parameters
658 * @rch: Indicate whether this dport was enumerated in RCH or VH mode
659 * @port: reference to cxl_port that contains this downstream port
662 * @hb_coord: access coordinates (performance) from ACPI generic port (host bridge)
671 struct cxl_port *port; member
679 * struct cxl_ep - track an endpoint's interest in a port
681 * @dport: which dport routes to this endpoint on @port
682 * @next: cxl switch port across the link attached to @dport NULL if
692 * struct cxl_region_ref - track a region's interest in a port
693 * @port: point in topology to install this reference
694 * @decoder: decoder assigned for @region in @port
696 * @endpoints: cxl_ep references for region members beneath @port
698 * @nr_eps: number of endpoints beneath @port
702 struct cxl_port *port; member
713 * CXL port topology. All other CXL ports have another CXL port as their
714 * parent and their ->uport_dev / host device is out-of-line of the port
717 static inline bool is_cxl_root(struct cxl_port *port) in is_cxl_root() argument
719 return port->uport_dev == port->dev.parent; in is_cxl_root()
722 int cxl_num_decoders_committed(struct cxl_port *port);
728 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port);
735 struct cxl_root *find_cxl_root(struct cxl_port *port);
748 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
751 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port,
769 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
773 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
776 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port);
782 * struct cxl_endpoint_dvsec_info - Cached DVSEC info
785 * @port: endpoint port associated with this info instance
791 struct cxl_port *port; member
796 struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
800 int devm_cxl_add_passthrough_decoder(struct cxl_port *port);
844 struct cxl_port *port);
877 void cxl_endpoint_parse_cdat(struct cxl_port *port);
878 void cxl_switch_parse_cdat(struct cxl_port *port);
880 int cxl_endpoint_get_perf_coordinates(struct cxl_port *port,