Lines Matching +full:y +full:- +full:rc
1 // SPDX-License-Identifier: GPL-2.0-only
25 struct acpi_cdat_header *hdr = &header->cdat; in cdat_dsmas_handler()
31 int rc; in cdat_dsmas_handler() local
33 len = le16_to_cpu((__force __le16)hdr->length); in cdat_dsmas_handler()
36 return -EINVAL; in cdat_dsmas_handler()
44 return -ENOMEM; in cdat_dsmas_handler()
46 dent->handle = dsmas->dsmad_handle; in cdat_dsmas_handler()
47 dent->dpa_range.start = le64_to_cpu((__force __le64)dsmas->dpa_base_address); in cdat_dsmas_handler()
48 dent->dpa_range.end = le64_to_cpu((__force __le64)dsmas->dpa_base_address) + in cdat_dsmas_handler()
49 le64_to_cpu((__force __le64)dsmas->dpa_length) - 1; in cdat_dsmas_handler()
51 rc = xa_insert(dsmas_xa, dent->handle, dent, GFP_KERNEL); in cdat_dsmas_handler()
52 if (rc) { in cdat_dsmas_handler()
54 return rc; in cdat_dsmas_handler()
65 coord->read_latency = val; in cxl_access_coordinate_set()
66 coord->write_latency = val; in cxl_access_coordinate_set()
69 coord->read_latency = val; in cxl_access_coordinate_set()
72 coord->write_latency = val; in cxl_access_coordinate_set()
75 coord->read_bandwidth = val; in cxl_access_coordinate_set()
76 coord->write_bandwidth = val; in cxl_access_coordinate_set()
79 coord->read_bandwidth = val; in cxl_access_coordinate_set()
82 coord->write_bandwidth = val; in cxl_access_coordinate_set()
90 struct acpi_cdat_header *hdr = &header->cdat; in cdat_dslbis_handler()
99 int rc; in cdat_dslbis_handler() local
101 len = le16_to_cpu((__force __le16)hdr->length); in cdat_dslbis_handler()
104 return -EINVAL; in cdat_dslbis_handler()
111 if (dslbis->data_type > ACPI_HMAT_WRITE_BANDWIDTH) in cdat_dslbis_handler()
115 if ((dslbis->flags & ACPI_HMAT_MEMORY_HIERARCHY) != ACPI_HMAT_MEMORY) in cdat_dslbis_handler()
118 dent = xa_load(dsmas_xa, dslbis->handle); in cdat_dslbis_handler()
124 le_base = (__force __le64)dslbis->entry_base_unit; in cdat_dslbis_handler()
125 le_val = (__force __le16)dslbis->entry[0]; in cdat_dslbis_handler()
126 rc = check_mul_overflow(le64_to_cpu(le_base), in cdat_dslbis_handler()
128 if (rc) in cdat_dslbis_handler()
131 cxl_access_coordinate_set(&dent->coord, dslbis->data_type, val); in cdat_dslbis_handler()
136 static int cdat_table_parse_output(int rc) in cdat_table_parse_output() argument
138 if (rc < 0) in cdat_table_parse_output()
139 return rc; in cdat_table_parse_output()
140 if (rc == 0) in cdat_table_parse_output()
141 return -ENOENT; in cdat_table_parse_output()
149 int rc; in cxl_cdat_endpoint_process() local
151 rc = cdat_table_parse(ACPI_CDAT_TYPE_DSMAS, cdat_dsmas_handler, in cxl_cdat_endpoint_process()
152 dsmas_xa, port->cdat.table); in cxl_cdat_endpoint_process()
153 rc = cdat_table_parse_output(rc); in cxl_cdat_endpoint_process()
154 if (rc) in cxl_cdat_endpoint_process()
155 return rc; in cxl_cdat_endpoint_process()
157 rc = cdat_table_parse(ACPI_CDAT_TYPE_DSLBIS, cdat_dslbis_handler, in cxl_cdat_endpoint_process()
158 dsmas_xa, port->cdat.table); in cxl_cdat_endpoint_process()
159 return cdat_table_parse_output(rc); in cxl_cdat_endpoint_process()
169 int rc; in cxl_port_perf_data_calculate() local
171 rc = cxl_endpoint_get_perf_coordinates(port, &c); in cxl_port_perf_data_calculate()
172 if (rc) { in cxl_port_perf_data_calculate()
173 dev_dbg(&port->dev, "Failed to retrieve perf coordinates.\n"); in cxl_port_perf_data_calculate()
174 return rc; in cxl_port_perf_data_calculate()
180 return -ENODEV; in cxl_port_perf_data_calculate()
182 if (!cxl_root->ops || !cxl_root->ops->qos_class) in cxl_port_perf_data_calculate()
183 return -EOPNOTSUPP; in cxl_port_perf_data_calculate()
188 dent->coord.read_latency = dent->coord.read_latency + in cxl_port_perf_data_calculate()
190 dent->coord.write_latency = dent->coord.write_latency + in cxl_port_perf_data_calculate()
192 dent->coord.read_bandwidth = min_t(int, c.read_bandwidth, in cxl_port_perf_data_calculate()
193 dent->coord.read_bandwidth); in cxl_port_perf_data_calculate()
194 dent->coord.write_bandwidth = min_t(int, c.write_bandwidth, in cxl_port_perf_data_calculate()
195 dent->coord.write_bandwidth); in cxl_port_perf_data_calculate()
197 dent->entries = 1; in cxl_port_perf_data_calculate()
198 rc = cxl_root->ops->qos_class(cxl_root, &dent->coord, 1, in cxl_port_perf_data_calculate()
200 if (rc != 1) in cxl_port_perf_data_calculate()
204 dent->qos_class = qos_class; in cxl_port_perf_data_calculate()
208 return -ENOENT; in cxl_port_perf_data_calculate()
216 dpa_perf->dpa_range = dent->dpa_range; in update_perf_entry()
217 dpa_perf->coord = dent->coord; in update_perf_entry()
218 dpa_perf->qos_class = dent->qos_class; in update_perf_entry()
221 dent->dpa_range.start, dpa_perf->qos_class, in update_perf_entry()
222 dent->coord.read_bandwidth, dent->coord.write_bandwidth, in update_perf_entry()
223 dent->coord.read_latency, dent->coord.write_latency); in update_perf_entry()
230 struct device *dev = cxlds->dev; in cxl_memdev_set_qos_class()
232 .start = cxlds->pmem_res.start, in cxl_memdev_set_qos_class()
233 .end = cxlds->pmem_res.end, in cxl_memdev_set_qos_class()
236 .start = cxlds->ram_res.start, in cxl_memdev_set_qos_class()
237 .end = cxlds->ram_res.end, in cxl_memdev_set_qos_class()
243 if (resource_size(&cxlds->ram_res) && in cxl_memdev_set_qos_class()
244 range_contains(&ram_range, &dent->dpa_range)) in cxl_memdev_set_qos_class()
245 update_perf_entry(dev, dent, &mds->ram_perf); in cxl_memdev_set_qos_class()
246 else if (resource_size(&cxlds->pmem_res) && in cxl_memdev_set_qos_class()
247 range_contains(&pmem_range, &dent->dpa_range)) in cxl_memdev_set_qos_class()
248 update_perf_entry(dev, dent, &mds->pmem_perf); in cxl_memdev_set_qos_class()
251 dent->dpa_range.start); in cxl_memdev_set_qos_class()
264 if (cxlrd->qos_class == CXL_QOS_CLASS_INVALID) in match_cxlrd_qos_class()
267 if (cxlrd->qos_class == dev_qos_class) in match_cxlrd_qos_class()
283 if (dpa_perf->qos_class == CXL_QOS_CLASS_INVALID) in cxl_qos_match()
286 if (!device_for_each_child(&root_port->dev, &dpa_perf->qos_class, in cxl_qos_match()
303 cxlsd = &cxlrd->cxlsd; in match_cxlrd_hb()
306 for (int i = 0; i < cxlsd->nr_targets; i++) { in match_cxlrd_hb()
307 if (host_bridge == cxlsd->target[i]->dport_dev) in match_cxlrd_hb()
316 struct cxl_dev_state *cxlds = cxlmd->cxlds; in cxl_qos_class_verify()
319 int rc; in cxl_qos_class_verify() local
322 find_cxl_root(cxlmd->endpoint); in cxl_qos_class_verify()
325 return -ENODEV; in cxl_qos_class_verify()
327 root_port = &cxl_root->port; in cxl_qos_class_verify()
330 if (!cxl_qos_match(root_port, &mds->ram_perf)) in cxl_qos_class_verify()
331 reset_dpa_perf(&mds->ram_perf); in cxl_qos_class_verify()
332 if (!cxl_qos_match(root_port, &mds->pmem_perf)) in cxl_qos_class_verify()
333 reset_dpa_perf(&mds->pmem_perf); in cxl_qos_class_verify()
336 rc = device_for_each_child(&root_port->dev, in cxl_qos_class_verify()
337 cxlmd->endpoint->host_bridge, match_cxlrd_hb); in cxl_qos_class_verify()
338 if (!rc) { in cxl_qos_class_verify()
339 reset_dpa_perf(&mds->ram_perf); in cxl_qos_class_verify()
340 reset_dpa_perf(&mds->pmem_perf); in cxl_qos_class_verify()
343 return rc; in cxl_qos_class_verify()
361 struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev); in DEFINE_FREE()
362 struct cxl_dev_state *cxlds = cxlmd->cxlds; in DEFINE_FREE()
365 int rc; in DEFINE_FREE() local
368 if (!port->cdat.table) in DEFINE_FREE()
371 rc = cxl_cdat_endpoint_process(port, dsmas_xa); in DEFINE_FREE()
372 if (rc < 0) { in DEFINE_FREE()
373 dev_dbg(&port->dev, "Failed to parse CDAT: %d\n", rc); in DEFINE_FREE()
377 rc = cxl_port_perf_data_calculate(port, dsmas_xa); in DEFINE_FREE()
378 if (rc) { in DEFINE_FREE()
379 dev_dbg(&port->dev, "Failed to do perf coord calculations.\n"); in DEFINE_FREE()
393 int size = sizeof(header->cdat) + sizeof(*sslbis); in cdat_sslbis_handler()
395 struct device *dev = &port->dev; in cdat_sslbis_handler()
400 len = le16_to_cpu((__force __le16)header->cdat.length); in cdat_sslbis_handler()
401 remain = len - size; in cdat_sslbis_handler()
405 return -EINVAL; in cdat_sslbis_handler()
410 sizeof(header->cdat)); in cdat_sslbis_handler()
413 if (sslbis->data_type > ACPI_HMAT_WRITE_BANDWIDTH) in cdat_sslbis_handler()
420 u16 x = le16_to_cpu((__force __le16)entry->portx_id); in cdat_sslbis_handler()
421 u16 y = le16_to_cpu((__force __le16)entry->porty_id); in cdat_sslbis_handler() local
431 dsp_id = y; in cdat_sslbis_handler()
434 switch (y) { in cdat_sslbis_handler()
442 dsp_id = y; in cdat_sslbis_handler()
451 le_base = (__force __le64)sslbis->entry_base_unit; in cdat_sslbis_handler()
452 le_val = (__force __le16)entry->latency_or_bandwidth; in cdat_sslbis_handler()
458 xa_for_each(&port->dports, index, dport) { in cdat_sslbis_handler()
460 dsp_id == dport->port_id) in cdat_sslbis_handler()
461 cxl_access_coordinate_set(&dport->sw_coord, in cdat_sslbis_handler()
462 sslbis->data_type, in cdat_sslbis_handler()
474 int rc; in cxl_switch_parse_cdat() local
476 if (!port->cdat.table) in cxl_switch_parse_cdat()
479 rc = cdat_table_parse(ACPI_CDAT_TYPE_SSLBIS, cdat_sslbis_handler, in cxl_switch_parse_cdat()
480 port, port->cdat.table); in cxl_switch_parse_cdat()
481 rc = cdat_table_parse_output(rc); in cxl_switch_parse_cdat()
482 if (rc) in cxl_switch_parse_cdat()
483 dev_dbg(&port->dev, "Failed to parse SSLBIS: %d\n", rc); in cxl_switch_parse_cdat()