Lines Matching +full:memory +full:- +full:to +full:- +full:memory
1 # SPDX-License-Identifier: GPL-2.0-only
12 CXL.mem). The CXL.cache protocol allows devices to hold cachelines
13 locally, the CXL.mem protocol allows devices to be fully coherent
14 memory targets, the CXL.io protocol is equivalent to PCI Express.
15 Say 'y' to enable support for the configuration and management of
24 The CXL specification defines a "CXL memory device" sub-class in the
25 PCI "memory controller" base class of devices. Device's identified by
27 memory to be mapped into the system address map (Host-managed Device
28 Memory (HDM)).
30 Say 'y/m' to enable a driver that will attach to CXL memory expander
31 devices enumerated by the memory device class code for configuration
38 bool "RAW Command Interface for Memory Devices"
49 the driver it is useful to be able to submit any possible command to
50 the hardware, even commands that may crash the kernel due to their
51 potential impact to memory currently in use by the kernel.
63 Enable support for host managed device memory (HDM) resources
64 published by a platform's ACPI CXL memory layout description. See
66 specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)
67 (https://www.computeexpresslink.org/spec-landing). The CXL core
68 consumes these resource to publish the root of a cxl_port decode
69 hierarchy to map regions that represent System RAM, or Persistent
70 Memory regions to be managed by LIBNVDIMM.
75 tristate "CXL PMEM: Persistent Memory Support"
79 In addition to typical memory resources a platform may also advertise
80 support for persistent memory attached via CXL. This support is
81 managed via a bridge driver from CXL to the LIBNVDIMM system
82 subsystem. Say 'y/m' to enable support for enumerating and
83 provisioning the persistent memory capacity of CXL memory expanders.
88 tristate "CXL: Memory Expansion"
92 The CXL.mem protocol allows a device to act as a provider of "System
93 RAM" and/or "Persistent Memory" that is fully coherent as if the
94 memory were attached to the typical CPU memory controller. This is
95 known as HDM "Host-managed Device Memory".
97 Say 'y/m' to enable a driver that will attach to CXL.mem devices for
98 memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0
119 Enable the CXL core to enumerate and provision CXL regions. A CXL
121 system-physical address range. For CXL regions established by
122 platform-firmware this option enables memory error handling to
123 identify the devices participating in a given interleaved memory
124 range. Otherwise, platform-firmware managed CXL is enabled by being
134 the content of CPU caches without notifying those caches to
136 to invalidate caches when those events occur. If that invalidation
137 fails the region will fail to enable. Reasons for cache
138 invalidation failure are due to the CPU not providing a cache
139 invalidation mechanism. For example usage of wbinvd is restricted to
156 Say 'y/m' to enable a driver that will attach to performance