1 /* SPDX-License-Identifier: GPL-2.0-only
20  * CPT instruction queue size passed to HW is in units of 40*CPT_INST_S
28 #define OTX2_CPT_INST_QLEN_MSGS	((OTX2_CPT_SIZE_DIV40 - 1) * 40)
33  * size by 320 and give 320 entries less for SW/NIX RX as a workaround.
73 	u32 size;  member
87 	int msix_offset;                        /* MSI-X interrupts offset */
91 	u8 slot;                                /* Slot number of this LF */  member
123 	int global_slot;        /* Global slot across the blocks */
134 	for (i = 0; i < lfs->lfs_num; i++) {  in otx2_cpt_free_instruction_queues()
135 		iq = &lfs->lf[i].iqueue;  in otx2_cpt_free_instruction_queues()
136 		if (iq->real_vaddr)  in otx2_cpt_free_instruction_queues()
137 			dma_free_coherent(&lfs->pdev->dev,  in otx2_cpt_free_instruction_queues()
138 					  iq->size,  in otx2_cpt_free_instruction_queues()
139 					  iq->real_vaddr,  in otx2_cpt_free_instruction_queues()
140 					  iq->real_dma_addr);  in otx2_cpt_free_instruction_queues()
141 		iq->real_vaddr = NULL;  in otx2_cpt_free_instruction_queues()
142 		iq->vaddr = NULL;  in otx2_cpt_free_instruction_queues()
152 	if (!lfs->lfs_num)  in otx2_cpt_alloc_instruction_queues()
153 		return -EINVAL;  in otx2_cpt_alloc_instruction_queues()
155 	for (i = 0; i < lfs->lfs_num; i++) {  in otx2_cpt_alloc_instruction_queues()
156 		iq = &lfs->lf[i].iqueue;  in otx2_cpt_alloc_instruction_queues()
157 		iq->size = OTX2_CPT_INST_QLEN_BYTES +  in otx2_cpt_alloc_instruction_queues()
161 		iq->real_vaddr = dma_alloc_coherent(&lfs->pdev->dev, iq->size,  in otx2_cpt_alloc_instruction_queues()
162 					&iq->real_dma_addr, GFP_KERNEL);  in otx2_cpt_alloc_instruction_queues()
163 		if (!iq->real_vaddr) {  in otx2_cpt_alloc_instruction_queues()
164 			ret = -ENOMEM;  in otx2_cpt_alloc_instruction_queues()
167 		iq->vaddr = iq->real_vaddr + OTX2_CPT_INST_GRP_QLEN_BYTES;  in otx2_cpt_alloc_instruction_queues()
168 		iq->dma_addr = iq->real_dma_addr + OTX2_CPT_INST_GRP_QLEN_BYTES;  in otx2_cpt_alloc_instruction_queues()
171 		iq->vaddr = PTR_ALIGN(iq->vaddr, OTX2_CPT_INST_Q_ALIGNMENT);  in otx2_cpt_alloc_instruction_queues()
172 		iq->dma_addr = PTR_ALIGN(iq->dma_addr,  in otx2_cpt_alloc_instruction_queues()
186 	int slot;  in otx2_cptlf_set_iqueues_base_addr()  local
188 	for (slot = 0; slot < lfs->lfs_num; slot++) {  in otx2_cptlf_set_iqueues_base_addr()
189 		lf_q_base.u = lfs->lf[slot].iqueue.dma_addr;  in otx2_cptlf_set_iqueues_base_addr()
190 		otx2_cpt_write64(lfs->reg_base, lfs->blkaddr, slot,  in otx2_cptlf_set_iqueues_base_addr()
201 	otx2_cpt_write64(lf->lfs->reg_base, lf->lfs->blkaddr, lf->slot,  in otx2_cptlf_do_set_iqueue_size()
207 	int slot;  in otx2_cptlf_set_iqueues_size()  local
209 	for (slot = 0; slot < lfs->lfs_num; slot++)  in otx2_cptlf_set_iqueues_size()
210 		otx2_cptlf_do_set_iqueue_size(&lfs->lf[slot]);  in otx2_cptlf_set_iqueues_size()
222 	void __iomem *reg_base = lf->lfs->reg_base;  in otx2_cptlf_do_disable_iqueue()
223 	struct pci_dev *pdev = lf->lfs->pdev;  in otx2_cptlf_do_disable_iqueue()
224 	u8 blkaddr = lf->lfs->blkaddr;  in otx2_cptlf_do_disable_iqueue()
227 	u64 slot = lf->slot;  in otx2_cptlf_do_disable_iqueue()  local
232 	otx2_cpt_write64(reg_base, blkaddr, slot, OTX2_CPT_LF_CTL, 0x0);  in otx2_cptlf_do_disable_iqueue()
234 	inprog = otx2_cpt_read64(reg_base, blkaddr, slot, OTX2_CPT_LF_INPROG);  in otx2_cptlf_do_disable_iqueue()
236 	otx2_cpt_write64(reg_base, blkaddr, slot, OTX2_CPT_LF_INPROG, inprog);  in otx2_cptlf_do_disable_iqueue()
238 	qsize = otx2_cpt_read64(reg_base, blkaddr, slot, OTX2_CPT_LF_Q_SIZE) & 0x7FFF;  in otx2_cptlf_do_disable_iqueue()
240 		inst_ptr = otx2_cpt_read64(reg_base, blkaddr, slot, OTX2_CPT_LF_Q_INST_PTR);  in otx2_cptlf_do_disable_iqueue()
242 			  FIELD_GET(NQPTR, inst_ptr) - FIELD_GET(DQPTR, inst_ptr);  in otx2_cptlf_do_disable_iqueue()
244 		timeout--;  in otx2_cptlf_do_disable_iqueue()
248 		dev_warn(&pdev->dev, "TIMEOUT: CPT poll on pending instructions\n");  in otx2_cptlf_do_disable_iqueue()
251 	/* Wait for CPT queue to become execution-quiescent */  in otx2_cptlf_do_disable_iqueue()
253 		inprog = otx2_cpt_read64(reg_base, blkaddr, slot, OTX2_CPT_LF_INPROG);  in otx2_cptlf_do_disable_iqueue()
260 			timeout--;  in otx2_cptlf_do_disable_iqueue()
265 		dev_warn(&pdev->dev, "TIMEOUT: CPT poll on inflight count\n");  in otx2_cptlf_do_disable_iqueue()
272 	int slot;  in otx2_cptlf_disable_iqueues()  local
274 	for (slot = 0; slot < lfs->lfs_num; slot++) {  in otx2_cptlf_disable_iqueues()
275 		otx2_cptlf_do_disable_iqueue(&lfs->lf[slot]);  in otx2_cptlf_disable_iqueues()
276 		otx2_cpt_lf_reset_msg(lfs, lfs->global_slot + slot);  in otx2_cptlf_disable_iqueues()
283 	u8 blkaddr = lf->lfs->blkaddr;  in otx2_cptlf_set_iqueue_enq()
286 	lf_ctl.u = otx2_cpt_read64(lf->lfs->reg_base, blkaddr, lf->slot,  in otx2_cptlf_set_iqueue_enq()
291 	otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,  in otx2_cptlf_set_iqueue_enq()
304 	u8 blkaddr = lf->lfs->blkaddr;  in otx2_cptlf_set_iqueue_exec()
306 	lf_inprog.u = otx2_cpt_read64(lf->lfs->reg_base, blkaddr, lf->slot,  in otx2_cptlf_set_iqueue_exec()
311 	otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,  in otx2_cptlf_set_iqueue_exec()
317 	u8 blkaddr = lf->lfs->blkaddr;  in otx2_cptlf_set_ctx_flr_flush()
320 	val = otx2_cpt_read64(lf->lfs->reg_base, blkaddr, lf->slot,  in otx2_cptlf_set_ctx_flr_flush()
324 	otx2_cpt_write64(lf->lfs->reg_base, blkaddr, lf->slot,  in otx2_cptlf_set_ctx_flr_flush()
340 	int slot;  in otx2_cptlf_enable_iqueues()  local
342 	for (slot = 0; slot < lfs->lfs_num; slot++) {  in otx2_cptlf_enable_iqueues()
344 		if (is_dev_cn10kb(lfs->pdev))  in otx2_cptlf_enable_iqueues()
345 			otx2_cptlf_set_ctx_flr_flush(&lfs->lf[slot]);  in otx2_cptlf_enable_iqueues()
347 		otx2_cptlf_enable_iqueue_exec(&lfs->lf[slot]);  in otx2_cptlf_enable_iqueues()
348 		otx2_cptlf_enable_iqueue_enq(&lfs->lf[slot]);  in otx2_cptlf_enable_iqueues()
356 	cptinst->u[0] = 0x0;  in otx2_cpt_fill_inst()
357 	cptinst->s.doneint = true;  in otx2_cpt_fill_inst()
358 	cptinst->s.res_addr = comp_baddr;  in otx2_cpt_fill_inst()
359 	cptinst->u[2] = 0x0;  in otx2_cpt_fill_inst()
360 	cptinst->u[3] = 0x0;  in otx2_cpt_fill_inst()
361 	cptinst->s.ei0 = iq_cmd->cmd.u;  in otx2_cpt_fill_inst()
362 	cptinst->s.ei1 = iq_cmd->dptr;  in otx2_cpt_fill_inst()
363 	cptinst->s.ei2 = iq_cmd->rptr;  in otx2_cpt_fill_inst()
364 	cptinst->s.ei3 = iq_cmd->cptr.u;  in otx2_cpt_fill_inst()
370  * 1 - 1 CPT instruction will be enqueued during LMTST operation
371  * 2 - 2 CPT instructions will be enqueued during LMTST operation
376 	void __iomem *lmtline = lf->lmtline;  in otx2_cpt_send_cmd()
393 		 * - No stores have been performed to the LMTLINE since it was  in otx2_cpt_send_cmd()
395 		 * - The bytes which have been stored to LMTLINE since it was  in otx2_cpt_send_cmd()
396 		 * last invalidated form a pattern that is non-contiguous, does  in otx2_cpt_send_cmd()
397 		 * not start at byte 0, or does not end on a 8-byte boundary.  in otx2_cpt_send_cmd()
398 		 * (i.e.comprises a formation of other than 1–16 8-byte  in otx2_cpt_send_cmd()
407 		ret = otx2_lmt_flush(lf->ioreg);  in otx2_cpt_send_cmd()
414 	return atomic_read(&lfs->state) == OTX2_CPTLF_STARTED;  in otx2_cptlf_started()
423 	lfs->pdev = pdev;  in otx2_cptlf_set_dev_info()
424 	lfs->reg_base = reg_base;  in otx2_cptlf_set_dev_info()
425 	lfs->mbox = mbox;  in otx2_cptlf_set_dev_info()
426 	lfs->blkaddr = blkaddr;  in otx2_cptlf_set_dev_info()