Lines Matching +full:sec +full:- +full:era
1 // SPDX-License-Identifier: GPL-2.0+
2 /* * CAAM control-plane driver backend
3 * Controller-level driver, kernel property detection, initialization
5 * Copyright 2008-2012 Freescale Semiconductor, Inc.
6 * Copyright 2018-2019, 2023 NXP
45 /* INIT RNG in non-test mode */ in build_instantiation_desc()
93 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
95 * @ctrldev - pointer to device
96 * @status - descriptor status, after being run
98 * Return: - 0 if no error occurred
99 * - -ENODEV if the DECO couldn't be acquired
100 * - -EAGAIN if an error occurred while executing the descriptor
106 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; in run_descriptor_deco0()
107 struct caam_deco __iomem *deco = ctrlpriv->deco; in run_descriptor_deco0()
113 if (ctrlpriv->virt_en == 1 || in run_descriptor_deco0()
119 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0); in run_descriptor_deco0()
121 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) && in run_descriptor_deco0()
122 --timeout) in run_descriptor_deco0()
128 clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE); in run_descriptor_deco0()
130 while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) && in run_descriptor_deco0()
131 --timeout) in run_descriptor_deco0()
136 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0); in run_descriptor_deco0()
137 return -ENODEV; in run_descriptor_deco0()
141 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i))); in run_descriptor_deco0()
152 clrsetbits_32(&deco->jr_ctl_hi, 0, flags); in run_descriptor_deco0()
156 deco_dbg_reg = rd_reg32(&deco->desc_dbg); in run_descriptor_deco0()
158 if (ctrlpriv->era < 10) in run_descriptor_deco0()
162 deco_state = (rd_reg32(&deco->dbg_exec) & in run_descriptor_deco0()
174 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout); in run_descriptor_deco0()
176 *status = rd_reg32(&deco->op_status_hi) & in run_descriptor_deco0()
179 if (ctrlpriv->virt_en == 1) in run_descriptor_deco0()
180 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0); in run_descriptor_deco0()
183 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0); in run_descriptor_deco0()
186 return -EAGAIN; in run_descriptor_deco0()
192 * deinstantiate_rng - builds and executes a descriptor on DECO0,
194 * @ctrldev - pointer to device
195 * @state_handle_mask - bitmask containing the instantiation status
199 * Return: - 0 if no error occurred
200 * - -ENOMEM if there isn't enough memory to allocate the descriptor
201 * - -ENODEV if DECO0 couldn't be acquired
202 * - -EAGAIN if an error occurred when executing the descriptor
211 return -ENOMEM; in deinstantiate_rng()
251 * De-initialize RNG state handles initialized by this driver. in devm_deinstantiate_rng()
254 if (ctrlpriv->rng4_sh_init) in devm_deinstantiate_rng()
255 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init); in devm_deinstantiate_rng()
259 * instantiate_rng - builds and executes a descriptor on DECO0,
261 * @ctrldev - pointer to device
262 * @state_handle_mask - bitmask containing the instantiation status
266 * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK;
270 * Return: - 0 if no error occurred
271 * - -ENOMEM if there isn't enough memory to allocate the descriptor
272 * - -ENODEV if DECO0 couldn't be acquired
273 * - -EAGAIN if an error occurred when executing the descriptor
285 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; in instantiate_rng()
288 return -ENOMEM; in instantiate_rng()
333 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK; in instantiate_rng()
336 ret = -EAGAIN; in instantiate_rng()
352 * kick_trng - sets the various parameters for enabling the initialization
354 * @dev - pointer to the controller device
355 * @ent_delay - Defines the length (in system clocks) of each entropy sample.
364 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; in kick_trng()
365 r4tst = &ctrl->r4tst[0]; in kick_trng()
370 * force re-generation. in kick_trng()
372 clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM | RTMCTL_ACC); in kick_trng()
375 * Performance-wise, it does not make sense to in kick_trng()
380 rtsdctl = rd_reg32(&r4tst->rtsdctl); in kick_trng()
385 wr_reg32(&r4tst->rtfrqmin, val >> 2); in kick_trng()
387 wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE); in kick_trng()
390 wr_reg32(&r4tst->rtsdctl, (val << RTSDCTL_ENT_DLY_SHIFT) | in kick_trng()
394 * To avoid reprogramming the self-test parameters over and over again, in kick_trng()
398 wr_reg32(&r4tst->rtscmisc, (2 << 16) | 32); in kick_trng()
399 wr_reg32(&r4tst->rtpkrrng, 570); in kick_trng()
400 wr_reg32(&r4tst->rtpkrmax, 1600); in kick_trng()
401 wr_reg32(&r4tst->rtscml, (122 << 16) | 317); in kick_trng()
402 wr_reg32(&r4tst->rtscrl[0], (80 << 16) | 107); in kick_trng()
403 wr_reg32(&r4tst->rtscrl[1], (57 << 16) | 62); in kick_trng()
404 wr_reg32(&r4tst->rtscrl[2], (39 << 16) | 39); in kick_trng()
405 wr_reg32(&r4tst->rtscrl[3], (27 << 16) | 26); in kick_trng()
406 wr_reg32(&r4tst->rtscrl[4], (19 << 16) | 18); in kick_trng()
407 wr_reg32(&r4tst->rtscrl[5], (18 << 16) | 17); in kick_trng()
414 clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM | RTMCTL_ACC, in kick_trng()
423 u8 era; in caam_get_era_from_hw() member
440 u8 maj_rev, era; in caam_get_era_from_hw() local
444 ccbvid = rd_reg32(&perfmon->ccb_id); in caam_get_era_from_hw()
445 era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT; in caam_get_era_from_hw()
446 if (era) /* This is '0' prior to CAAM ERA-6 */ in caam_get_era_from_hw()
447 return era; in caam_get_era_from_hw()
449 id_ms = rd_reg32(&perfmon->caam_id_ms); in caam_get_era_from_hw()
455 return id[i].era; in caam_get_era_from_hw()
457 return -ENOTSUPP; in caam_get_era_from_hw()
461 * caam_get_era() - Return the ERA of the SEC on SoC, based
462 * on "sec-era" optional property in the DTS. This property is updated
463 * by u-boot.
465 * era via register reads will be made.
475 caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); in caam_get_era()
476 ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop); in caam_get_era()
505 .compatible = "fsl,sec-v4.0",
575 clk_bulk_disable_unprepare(ctrlpriv->num_clks, ctrlpriv->clks); in disable_clocks()
583 ctrlpriv->num_clks = data->num_clks; in init_clocks()
584 ctrlpriv->clks = devm_kmemdup(dev, data->clks, in init_clocks()
585 data->num_clks * sizeof(data->clks[0]), in init_clocks()
587 if (!ctrlpriv->clks) in init_clocks()
588 return -ENOMEM; in init_clocks()
590 ret = devm_clk_bulk_get(dev, ctrlpriv->num_clks, ctrlpriv->clks); in init_clocks()
597 ret = clk_bulk_prepare_enable(ctrlpriv->num_clks, ctrlpriv->clks); in init_clocks()
616 if (mc_version->major > major) in check_version()
619 if (mc_version->major == major) { in check_version()
620 if (mc_version->minor > minor) in check_version()
623 if (mc_version->minor == minor && in check_version()
624 mc_version->revision > revision) in check_version()
642 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; in caam_ctrl_rng_init()
646 if (ctrlpriv->era < 10) { in caam_ctrl_rng_init()
649 perfmon = ctrlpriv->total_jobrs ? in caam_ctrl_rng_init()
650 (struct caam_perfmon __iomem *)&ctrlpriv->jr[0]->perfmon : in caam_ctrl_rng_init()
651 (struct caam_perfmon __iomem *)&ctrl->perfmon; in caam_ctrl_rng_init()
653 rng_vid = (rd_reg32(&perfmon->cha_id_ls) & in caam_ctrl_rng_init()
658 vreg = ctrlpriv->total_jobrs ? in caam_ctrl_rng_init()
659 (struct version_regs __iomem *)&ctrlpriv->jr[0]->vreg : in caam_ctrl_rng_init()
660 (struct version_regs __iomem *)&ctrl->vreg; in caam_ctrl_rng_init()
662 rng_vid = (rd_reg32(&vreg->rng) & CHA_VER_VID_MASK) >> in caam_ctrl_rng_init()
667 * If SEC has RNG version >= 4 and RNG state handle has not been in caam_ctrl_rng_init()
671 if (!(ctrlpriv->mc_en && ctrlpriv->pr_support) && rng_vid >= 4) { in caam_ctrl_rng_init()
672 ctrlpriv->rng4_sh_init = in caam_ctrl_rng_init()
673 rd_reg32(&ctrl->r4tst[0].rdsta); in caam_ctrl_rng_init()
680 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1; in caam_ctrl_rng_init()
681 ctrlpriv->rng4_sh_init &= RDSTA_MASK; in caam_ctrl_rng_init()
684 rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK; in caam_ctrl_rng_init()
687 * (e.g. u-boot) then it is assumed that the entropy in caam_ctrl_rng_init()
695 if (!(ctrlpriv->rng4_sh_init || inst_handles)) { in caam_ctrl_rng_init()
720 if (ret == -EAGAIN) in caam_ctrl_rng_init()
726 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); in caam_ctrl_rng_init()
735 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_MASK; in caam_ctrl_rng_init()
738 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE); in caam_ctrl_rng_init()
757 struct caam_ctl_state *state = &ctrlpriv->state; in caam_state_save()
758 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; in caam_state_save()
762 state->mcr = rd_reg32(&ctrl->mcr); in caam_state_save()
763 state->scfgr = rd_reg32(&ctrl->scfgr); in caam_state_save()
765 deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) & in caam_state_save()
768 state->deco_mid[i].liodn_ms = in caam_state_save()
769 rd_reg32(&ctrl->deco_mid[i].liodn_ms); in caam_state_save()
770 state->deco_mid[i].liodn_ls = in caam_state_save()
771 rd_reg32(&ctrl->deco_mid[i].liodn_ls); in caam_state_save()
774 jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) & in caam_state_save()
777 state->jr_mid[i].liodn_ms = in caam_state_save()
778 rd_reg32(&ctrl->jr_mid[i].liodn_ms); in caam_state_save()
779 state->jr_mid[i].liodn_ls = in caam_state_save()
780 rd_reg32(&ctrl->jr_mid[i].liodn_ls); in caam_state_save()
787 const struct caam_ctl_state *state = &ctrlpriv->state; in caam_state_restore()
788 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; in caam_state_restore()
792 wr_reg32(&ctrl->mcr, state->mcr); in caam_state_restore()
793 wr_reg32(&ctrl->scfgr, state->scfgr); in caam_state_restore()
795 deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) & in caam_state_restore()
798 wr_reg32(&ctrl->deco_mid[i].liodn_ms, in caam_state_restore()
799 state->deco_mid[i].liodn_ms); in caam_state_restore()
800 wr_reg32(&ctrl->deco_mid[i].liodn_ls, in caam_state_restore()
801 state->deco_mid[i].liodn_ls); in caam_state_restore()
804 jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) & in caam_state_restore()
807 wr_reg32(&ctrl->jr_mid[i].liodn_ms, in caam_state_restore()
808 state->jr_mid[i].liodn_ms); in caam_state_restore()
809 wr_reg32(&ctrl->jr_mid[i].liodn_ls, in caam_state_restore()
810 state->jr_mid[i].liodn_ls); in caam_state_restore()
813 if (ctrlpriv->virt_en == 1) in caam_state_restore()
814 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START | in caam_state_restore()
823 if (ctrlpriv->caam_off_during_pm && !ctrlpriv->optee_en) in caam_ctrl_suspend()
834 if (ctrlpriv->caam_off_during_pm && !ctrlpriv->optee_en) { in caam_ctrl_resume()
864 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL); in caam_probe()
866 return -ENOMEM; in caam_probe()
868 dev = &pdev->dev; in caam_probe()
870 nprop = pdev->dev.of_node; in caam_probe()
874 return -EPROBE_DEFER; in caam_probe()
878 ctrlpriv->caam_off_during_pm = caam_imx && caam_off_during_pm(); in caam_probe()
882 * Until Layerscape and i.MX OP-TEE get in sync, in caam_probe()
883 * only i.MX OP-TEE use cases disallow access to in caam_probe()
886 np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz"); in caam_probe()
887 ctrlpriv->optee_en = !!np; in caam_probe()
890 reg_access = !ctrlpriv->optee_en; in caam_probe()
892 if (!imx_soc_match->data) { in caam_probe()
894 return -EINVAL; in caam_probe()
897 ret = init_clocks(dev, imx_soc_match->data); in caam_probe()
914 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || in caam_probe()
915 of_device_is_compatible(np, "fsl,sec4.0-job-ring")) { in caam_probe()
920 np->full_name); in caam_probe()
924 ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *) in caam_probe()
927 ctrlpriv->total_jobrs++; in caam_probe()
936 perfmon = ring ? (struct caam_perfmon __iomem *)&ctrlpriv->jr[0]->perfmon : in caam_probe()
937 (struct caam_perfmon __iomem *)&ctrl->perfmon; in caam_probe()
939 caam_little_end = !(bool)(rd_reg32(&perfmon->status) & in caam_probe()
941 comp_params = rd_reg32(&perfmon->comp_parms_ms); in caam_probe()
943 rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR) in caam_probe()
948 ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK); in caam_probe()
952 if (ctrlpriv->qi_present && !caam_dpaa2) { in caam_probe()
955 return -EPROBE_DEFER; in caam_probe()
958 return -ENODEV; in caam_probe()
963 return -EPROBE_DEFER; in caam_probe()
966 return -ENODEV; in caam_probe()
980 ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl; in caam_probe()
981 ctrlpriv->assure = (struct caam_assurance __iomem __force *) in caam_probe()
985 ctrlpriv->deco = (struct caam_deco __iomem __force *) in caam_probe()
991 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0); in caam_probe()
992 np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc"); in caam_probe()
993 ctrlpriv->mc_en = !!np; in caam_probe()
997 if (ctrlpriv->mc_en) { in caam_probe()
1002 ctrlpriv->pr_support = check_version(mc_version, 10, 20, in caam_probe()
1005 return -EPROBE_DEFER; in caam_probe()
1018 if (!ctrlpriv->mc_en) in caam_probe()
1019 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK, in caam_probe()
1023 handle_imx6_err005766(&ctrl->mcr); in caam_probe()
1029 scfgr = rd_reg32(&ctrl->scfgr); in caam_probe()
1031 ctrlpriv->virt_en = 0; in caam_probe()
1039 ctrlpriv->virt_en = 1; in caam_probe()
1043 ctrlpriv->virt_en = 1; in caam_probe()
1046 if (ctrlpriv->virt_en == 1) in caam_probe()
1047 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START | in caam_probe()
1058 ctrlpriv->era = caam_get_era(perfmon); in caam_probe()
1059 ctrlpriv->domain = iommu_get_domain_for_dev(dev); in caam_probe()
1072 if (ctrlpriv->qi_present && !caam_dpaa2) { in caam_probe()
1073 ctrlpriv->qi = (struct caam_queue_if __iomem __force *) in caam_probe()
1078 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN); in caam_probe()
1080 /* If QMAN driver is present, init CAAM-QI backend */ in caam_probe()
1089 if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) { in caam_probe()
1091 return -ENOMEM; in caam_probe()
1094 comp_params = rd_reg32(&perfmon->comp_parms_ls); in caam_probe()
1095 ctrlpriv->blob_present = !!(comp_params & CTPR_LS_BLOB); in caam_probe()
1098 * Some SoCs like the LS1028A (non-E) indicate CTPR_LS_BLOB support, in caam_probe()
1102 if (ctrlpriv->era < 10) { in caam_probe()
1103 ctrlpriv->blob_present = ctrlpriv->blob_present && in caam_probe()
1104 (rd_reg32(&perfmon->cha_num_ls) & CHA_ID_LS_AES_MASK); in caam_probe()
1108 vreg = ctrlpriv->total_jobrs ? in caam_probe()
1109 (struct version_regs __iomem *)&ctrlpriv->jr[0]->vreg : in caam_probe()
1110 (struct version_regs __iomem *)&ctrl->vreg; in caam_probe()
1112 ctrlpriv->blob_present = ctrlpriv->blob_present && in caam_probe()
1113 (rd_reg32(&vreg->aesa) & CHA_VER_MISC_AES_NUM_MASK); in caam_probe()
1122 caam_id = (u64)rd_reg32(&perfmon->caam_id_ms) << 32 | in caam_probe()
1123 (u64)rd_reg32(&perfmon->caam_id_ls); in caam_probe()
1126 dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, in caam_probe()
1127 ctrlpriv->era); in caam_probe()
1129 ctrlpriv->total_jobrs, ctrlpriv->qi_present); in caam_probe()
1151 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");