Lines Matching +full:processing +full:- +full:engine
1 # SPDX-License-Identifier: GPL-2.0-only
20 Some VIA processors come with an integrated crypto engine
21 (so called VIA PadLock ACE, Advanced Cryptography Engine)
39 called padlock-aes.
53 called padlock-sha.
56 tristate "Support for the Geode LX AES engine"
61 Say 'Y' here to use the AMD Geode LX processor on-board AES
62 engine for the CryptoAPI AES algorithm.
65 will be called geode-aes.
131 and uses triple-DES to generate secure random numbers like the
132 ANSI X9.17 standard. User-space programs access the
133 pseudo-random-number device through the char device /dev/prandom.
138 tristate "Niagara2 Stream Processing Unit driver"
148 Processing Unit, which itself contains several cryptographic
149 sub-units. One set provides the Modular Arithmetic Unit,
195 tristate "Talitos Freescale Security Engine (SEC)"
204 Say 'Y' here to use the Freescale Security Engine (SEC)
219 Say 'Y' here to use the Freescale Security Engine (SEC) version 1.0
220 found on MPC82xx or the Freescale Security Engine (SEC Lite)
228 Say 'Y' here to use the Freescale Security Engine (SEC)
250 This option provides the kernel-side support for the TRNG hardware
276 tristate "Support for OMAP AES hw engine"
290 tristate "Support for OMAP DES/3DES hw engine"
320 This driver provides kernel-side support through the
325 module will be called exynos-rng.
350 needed for small and zero-size messages.
391 will be called atmel-aes.
404 will be called atmel-tdes.
417 will be called atmel-sha.
435 will be called atmel-ecc.
450 will be called atmel-sha204a.
474 co-processor on the die.
477 will be called mxs-dcp.
492 tristate "Qualcomm crypto engine accelerator"
496 This driver supports Qualcomm crypto engine accelerator
529 (default), hashes-only, or skciphers-only.
531 The QCE engine does not appear to scale as well as the CPU to handle
532 multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the
536 algorithms, sharing the load with the CPU. Enabling skciphers-only
546 - AES (CBC, CTR, ECB, XTS)
547 - 3DES (CBC, ECB)
548 - DES (CBC, ECB)
549 - SHA1, HMAC-SHA1
550 - SHA256, HMAC-SHA256
553 bool "Symmetric-key ciphers only"
556 Enable symmetric-key ciphers only:
557 - AES (CBC, CTR, ECB, XTS)
558 - 3DES (ECB, CBC)
559 - DES (ECB, CBC)
566 - SHA1, HMAC-SHA1
567 - SHA256, HMAC-SHA256
574 - authenc()
575 - ccm(aes)
576 - rfc4309(ccm(aes))
585 using software instead of the crypto engine. It can be changed by
589 Considering the 256-bit ciphers, software is 2-3 times faster than
590 qce at 256-bytes, 30% faster at 512, and about even at 768-bytes.
591 With 128-bit keys, the break-even point would be around 1024-bytes.
594 cost in CPU usage. The minimum recommended setting is 16-bytes
595 (1 AES block), since AES-GCM will fail if you set it lower.
598 Note that 192-bit keys are not supported by the hardware and are
612 module will be called qcom-rng. If unsure, say N.
635 tristate "Rockchip's Cryptographic Engine driver"
671 Xilinx ZynqMP has AES-GCM engine used for symmetric key
681 Xilinx ZynqMP has SHA3 engine used for secure hash calculation.
682 This driver interfaces with SHA3 hardware engine.
703 Secure Processing Unit (SPU). The SPU driver registers skcipher,
709 tristate "Inside Secure's SafeXcel cryptographic engine driver"
724 This driver interfaces with the SafeXcel EIP-97 and EIP-197 cryptographic
728 Additionally, it accelerates combined AES-CBC/HMAC-SHA AEAD operations.
731 tristate "Support for Axis ARTPEC-6/7 hardware crypto acceleration."
744 Enables the driver for the on-chip crypto accelerator
795 K3 devices include a security accelerator engine that may be