drivers/cpufreq/ti-cpufreq.c

20 #define REVISION_MASK				0xF
23 #define AM33XX_800M_ARM_MPU_MAX_FREQ		0x1E2F
24 #define AM43XX_600M_ARM_MPU_MAX_FREQ		0xFFA
32 #define DRA7_EFUSE_NOM_MPU_OPP			BIT(0)
37 #define OMAP3_CONTROL_DEVICE_STATUS		0x4800244C
38 #define OMAP3_CONTROL_IDCODE			0x4830A204
39 #define OMAP34xx_ProdID_SKUID			0x4830A20C
40 #define OMAP3_SYSCON_BASE	(0x48000000 + 0x2000 + 0x270)
46 #define AM625_SUPPORT_K_MPU_OPP			BIT(0)
137 	.efuse_offset = 0x07fc,
138 	.efuse_mask = 0x1fff,
139 	.rev_offset = 0x600,
146 	.efuse_offset = 0x0610,
147 	.efuse_mask = 0x3f,
148 	.rev_offset = 0x600,
154 	.efuse_offset = 0x020c,
155 	.efuse_mask = 0xf80000,
157 	.rev_offset = 0x204,
163  *  CONTROL_IDCODE (0x4830 A204) describes Silicon revisions.
164  *  Control OMAP Status Register 15:0 (Address 0x4800 244C)
172  *  Register 0x4830A20C [ProdID.SKUID] [0:3]
173  *    0x0 for normal 600/430MHz device.
174  *    0x8 for 720/520MHz device.
189  *  CONTROL_IDCODE (0x4830 A204) describes Silicon revisions.
190  *  Control Device Status Register 15:0 (Address 0x4800 244C)
194  *     0 800/600 MHz
198  *  There is no 0x4830A20C [ProdID.SKUID] register (exists but
199  *    seems to always read as 0).
222 	.efuse_shift = 0,
223 	.efuse_mask = 0,
230 	.efuse_offset = 0x0018,
231 	.efuse_mask = 0x07c0,
232 	.efuse_shift = 0x6,
233 	.rev_offset = 0x0014,
275 	return 0;  in ti_cpufreq_get_efuse()
313 	return 0;  in ti_cpufreq_get_rev()
329 	return 0;  in ti_cpufreq_setup_syscon_register()
382 	opp_data->cpu_dev = get_cpu_device(0);  in ti_cpufreq_probe()
402 	 *	0 - SoC Revision  in ti_cpufreq_probe()
405 	ret = ti_cpufreq_get_rev(opp_data, &version[0]);  in ti_cpufreq_probe()
421 	if (ret < 0) {  in ti_cpufreq_probe()
429 	platform_device_register_simple("cpufreq-dt", -1, NULL, 0);  in ti_cpufreq_probe()
431 	return 0;  in ti_cpufreq_probe()
449 	return 0;  in ti_cpufreq_init()