1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk.h>
11 #include <linux/nvmem-consumer.h>
68 	old_freq = clk_get_rate(clks[ARM].clk) / 1000;  in imx6q_set_target()
81 	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",  in imx6q_set_target()
111 	 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change  in imx6q_set_target()
114 	 *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it  in imx6q_set_target()
115 	 *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it  in imx6q_set_target()
116 	 *  - Disable pll2_pfd2_396m_clk  in imx6q_set_target()
127 		clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);  in imx6q_set_target()
128 		clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);  in imx6q_set_target()
129 		if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk))  in imx6q_set_target()
130 			clk_set_parent(clks[SECONDARY_SEL].clk,  in imx6q_set_target()
131 				       clks[PLL2_BUS].clk);  in imx6q_set_target()
133 			clk_set_parent(clks[SECONDARY_SEL].clk,  in imx6q_set_target()
134 				       clks[PLL2_PFD2_396M].clk);  in imx6q_set_target()
135 		clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);  in imx6q_set_target()
136 		clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);  in imx6q_set_target()
137 		if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {  in imx6q_set_target()
138 			clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);  in imx6q_set_target()
139 			clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);  in imx6q_set_target()
142 		clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);  in imx6q_set_target()
143 		clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);  in imx6q_set_target()
144 		if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {  in imx6q_set_target()
145 			clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);  in imx6q_set_target()
146 			clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);  in imx6q_set_target()
148 			/* pll1_sys needs to be enabled for divider rate change to work. */  in imx6q_set_target()
150 			clk_prepare_enable(clks[PLL1_SYS].clk);  in imx6q_set_target()
155 	ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);  in imx6q_set_target()
159 		dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);  in imx6q_set_target()
167 	/* PLL1 is only needed until after ARM-PODF is set. */  in imx6q_set_target()
169 		clk_disable_unprepare(clks[PLL1_SYS].clk);  in imx6q_set_target()
192 	policy->clk = clks[ARM].clk;  in imx6q_cpufreq_init()
194 	policy->suspend_freq = max_freq;  in imx6q_cpufreq_init()
207 	.name = "imx6q-cpufreq",
216 	if (ret < 0 && ret != -ENODEV)  in imx6x_disable_freq_in_opp()
233 	if (of_property_present(dev->of_node, "nvmem-cells")) {  in imx6q_opp_check_speed_grading()
238 		np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");  in imx6q_opp_check_speed_grading()
240 			return -ENOENT;  in imx6q_opp_check_speed_grading()
246 			return -EFAULT;  in imx6q_opp_check_speed_grading()
250 		 * SPEED_GRADING[1:0] defines the max speed of ARM:  in imx6q_opp_check_speed_grading()
251 		 * 2b'11: 1200000000Hz;  in imx6q_opp_check_speed_grading()
252 		 * 2b'10: 996000000Hz;  in imx6q_opp_check_speed_grading()
253 		 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.  in imx6q_opp_check_speed_grading()
254 		 * 2b'00: 792000000Hz;  in imx6q_opp_check_speed_grading()
255 		 * We need to set the max speed of ARM according to fuse map.  in imx6q_opp_check_speed_grading()
288 	if (of_property_present(dev->of_node, "nvmem-cells")) {  in imx6ul_opp_check_speed_grading()
296 		np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");  in imx6ul_opp_check_speed_grading()
299 						     "fsl,imx6ull-ocotp");  in imx6ul_opp_check_speed_grading()
301 			return -ENOENT;  in imx6ul_opp_check_speed_grading()
307 			return -EFAULT;  in imx6ul_opp_check_speed_grading()
315 	 * Speed GRADING[1:0] defines the max speed of ARM:  in imx6ul_opp_check_speed_grading()
317 	 * 2b'01: 528000000Hz;  in imx6ul_opp_check_speed_grading()
318 	 * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;  in imx6ul_opp_check_speed_grading()
319 	 * 2b'11: 900000000Hz on i.MX6ULL only;  in imx6ul_opp_check_speed_grading()
320 	 * We need to set the max speed of ARM according to fuse map.  in imx6ul_opp_check_speed_grading()
353 		return -ENODEV;  in imx6q_cpufreq_probe()
356 	np = of_node_get(cpu_dev->of_node);  in imx6q_cpufreq_probe()
359 		return -ENOENT;  in imx6q_cpufreq_probe()
375 	if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||  in imx6q_cpufreq_probe()
376 			PTR_ERR(soc_reg) == -EPROBE_DEFER ||  in imx6q_cpufreq_probe()
377 			PTR_ERR(pu_reg) == -EPROBE_DEFER) {  in imx6q_cpufreq_probe()
378 		ret = -EPROBE_DEFER;  in imx6q_cpufreq_probe()
384 		ret = -ENOENT;  in imx6q_cpufreq_probe()
422 		ret = -ENOMEM;  in imx6q_cpufreq_probe()
426 	prop = of_find_property(np, "fsl,soc-operating-points", NULL);  in imx6q_cpufreq_probe()
427 	if (!prop || !prop->value)  in imx6q_cpufreq_probe()
432 	 * voltage like <freq-kHz vol-uV>.  in imx6q_cpufreq_probe()
434 	nr = prop->length / sizeof(u32);  in imx6q_cpufreq_probe()
439 		val = prop->value;  in imx6q_cpufreq_probe()
453 …dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!…  in imx6q_cpufreq_probe()
456 		if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)  in imx6q_cpufreq_probe()
457 			imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;  in imx6q_cpufreq_probe()
460 	if (of_property_read_u32(np, "clock-latency", &transition_latency))  in imx6q_cpufreq_probe()
464 	 * Calculate the ramp time for max voltage change in the  in imx6q_cpufreq_probe()
467 	ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);  in imx6q_cpufreq_probe()
471 		ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);  in imx6q_cpufreq_probe()
481 	max_freq = freq_table[--num].frequency;  in imx6q_cpufreq_probe()
537 		.name	= "imx6q-cpufreq",
544 MODULE_ALIAS("platform:imx6q-cpufreq");