1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2019-2021 Intel Corporation
11 #include <linux/counter.h>
32 #define INTEL_QEPCON_EDGE_A		BIT(2)
43 #define INTEL_QEPCON_INDX_PAH_PBL	INTEL_QEPCON_INDX_GATING(2)
47 #define INTEL_QEPCON_FIFO_THRE(n)	((((n) - 1) & 7) << 12)
57 #define INTEL_QEPINT_QEPRST_UP		BIT(2)
78 	return readl(qep->regs + offset);  in intel_qep_readl()
84 	writel(value, qep->regs + offset);  in intel_qep_writel()
94 	qep->enabled = false;  in intel_qep_init()
108 static int intel_qep_count_read(struct counter_device *counter,  in intel_qep_count_read()  argument
111 	struct intel_qep *const qep = counter_priv(counter);  in intel_qep_count_read()
113 	pm_runtime_get_sync(qep->dev);  in intel_qep_count_read()
115 	pm_runtime_put(qep->dev);  in intel_qep_count_read()
124 static int intel_qep_function_read(struct counter_device *counter,  in intel_qep_function_read()  argument
137 static int intel_qep_action_read(struct counter_device *counter,  in intel_qep_action_read()  argument
160 	INTEL_QEP_SIGNAL(2, "Index"),
172 	INTEL_QEP_SYNAPSE(2),
175 static int intel_qep_ceiling_read(struct counter_device *counter,  in intel_qep_ceiling_read()  argument
178 	struct intel_qep *qep = counter_priv(counter);  in intel_qep_ceiling_read()
180 	pm_runtime_get_sync(qep->dev);  in intel_qep_ceiling_read()
182 	pm_runtime_put(qep->dev);  in intel_qep_ceiling_read()
187 static int intel_qep_ceiling_write(struct counter_device *counter,  in intel_qep_ceiling_write()  argument
190 	struct intel_qep *qep = counter_priv(counter);  in intel_qep_ceiling_write()
193 	/* Intel QEP ceiling configuration only supports 32-bit values */  in intel_qep_ceiling_write()
195 		return -ERANGE;  in intel_qep_ceiling_write()
197 	mutex_lock(&qep->lock);  in intel_qep_ceiling_write()
198 	if (qep->enabled) {  in intel_qep_ceiling_write()
199 		ret = -EBUSY;  in intel_qep_ceiling_write()
203 	pm_runtime_get_sync(qep->dev);  in intel_qep_ceiling_write()
205 	pm_runtime_put(qep->dev);  in intel_qep_ceiling_write()
208 	mutex_unlock(&qep->lock);  in intel_qep_ceiling_write()
212 static int intel_qep_enable_read(struct counter_device *counter,  in intel_qep_enable_read()  argument
215 	struct intel_qep *qep = counter_priv(counter);  in intel_qep_enable_read()
217 	*enable = qep->enabled;  in intel_qep_enable_read()
222 static int intel_qep_enable_write(struct counter_device *counter,  in intel_qep_enable_write()  argument
225 	struct intel_qep *qep = counter_priv(counter);  in intel_qep_enable_write()
229 	mutex_lock(&qep->lock);  in intel_qep_enable_write()
230 	changed = val ^ qep->enabled;  in intel_qep_enable_write()
234 	pm_runtime_get_sync(qep->dev);  in intel_qep_enable_write()
239 		pm_runtime_get_noresume(qep->dev);  in intel_qep_enable_write()
242 		pm_runtime_put_noidle(qep->dev);  in intel_qep_enable_write()
246 	pm_runtime_put(qep->dev);  in intel_qep_enable_write()
247 	qep->enabled = val;  in intel_qep_enable_write()
250 	mutex_unlock(&qep->lock);  in intel_qep_enable_write()
254 static int intel_qep_spike_filter_ns_read(struct counter_device *counter,  in intel_qep_spike_filter_ns_read()  argument
258 	struct intel_qep *qep = counter_priv(counter);  in intel_qep_spike_filter_ns_read()
261 	pm_runtime_get_sync(qep->dev);  in intel_qep_spike_filter_ns_read()
264 		pm_runtime_put(qep->dev);  in intel_qep_spike_filter_ns_read()
268 	pm_runtime_put(qep->dev);  in intel_qep_spike_filter_ns_read()
270 	*length = (reg + 2) * INTEL_QEP_CLK_PERIOD_NS;  in intel_qep_spike_filter_ns_read()
275 static int intel_qep_spike_filter_ns_write(struct counter_device *counter,  in intel_qep_spike_filter_ns_write()  argument
279 	struct intel_qep *qep = counter_priv(counter);  in intel_qep_spike_filter_ns_write()
285 	 * Spike filter length is (MAX_COUNT + 2) clock periods.  in intel_qep_spike_filter_ns_write()
293 	} else if (length >= 2) {  in intel_qep_spike_filter_ns_write()
295 		length -= 2;  in intel_qep_spike_filter_ns_write()
297 		return -EINVAL;  in intel_qep_spike_filter_ns_write()
301 		return -ERANGE;  in intel_qep_spike_filter_ns_write()
303 	mutex_lock(&qep->lock);  in intel_qep_spike_filter_ns_write()
304 	if (qep->enabled) {  in intel_qep_spike_filter_ns_write()
305 		ret = -EBUSY;  in intel_qep_spike_filter_ns_write()
309 	pm_runtime_get_sync(qep->dev);  in intel_qep_spike_filter_ns_write()
317 	pm_runtime_put(qep->dev);  in intel_qep_spike_filter_ns_write()
320 	mutex_unlock(&qep->lock);  in intel_qep_spike_filter_ns_write()
324 static int intel_qep_preset_enable_read(struct counter_device *counter,  in intel_qep_preset_enable_read()  argument
328 	struct intel_qep *qep = counter_priv(counter);  in intel_qep_preset_enable_read()
331 	pm_runtime_get_sync(qep->dev);  in intel_qep_preset_enable_read()
333 	pm_runtime_put(qep->dev);  in intel_qep_preset_enable_read()
340 static int intel_qep_preset_enable_write(struct counter_device *counter,  in intel_qep_preset_enable_write()  argument
343 	struct intel_qep *qep = counter_priv(counter);  in intel_qep_preset_enable_write()
347 	mutex_lock(&qep->lock);  in intel_qep_preset_enable_write()
348 	if (qep->enabled) {  in intel_qep_preset_enable_write()
349 		ret = -EBUSY;  in intel_qep_preset_enable_write()
353 	pm_runtime_get_sync(qep->dev);  in intel_qep_preset_enable_write()
361 	pm_runtime_put(qep->dev);  in intel_qep_preset_enable_write()
364 	mutex_unlock(&qep->lock);  in intel_qep_preset_enable_write()
394 	struct counter_device *counter;  in intel_qep_probe()  local
396 	struct device *dev = &pci->dev;  in intel_qep_probe()
400 	counter = devm_counter_alloc(dev, sizeof(*qep));  in intel_qep_probe()
401 	if (!counter)  in intel_qep_probe()
402 		return -ENOMEM;  in intel_qep_probe()
403 	qep = counter_priv(counter);  in intel_qep_probe()
417 		return -ENOMEM;  in intel_qep_probe()
419 	qep->dev = dev;  in intel_qep_probe()
420 	qep->regs = regs;  in intel_qep_probe()
421 	mutex_init(&qep->lock);  in intel_qep_probe()
426 	counter->name = pci_name(pci);  in intel_qep_probe()
427 	counter->parent = dev;  in intel_qep_probe()
428 	counter->ops = &intel_qep_counter_ops;  in intel_qep_probe()
429 	counter->counts = intel_qep_counter_count;  in intel_qep_probe()
430 	counter->num_counts = ARRAY_SIZE(intel_qep_counter_count);  in intel_qep_probe()
431 	counter->signals = intel_qep_signals;  in intel_qep_probe()
432 	counter->num_signals = ARRAY_SIZE(intel_qep_signals);  in intel_qep_probe()
433 	qep->enabled = false;  in intel_qep_probe()
438 	ret = devm_counter_add(&pci->dev, counter);  in intel_qep_probe()
440 		return dev_err_probe(&pci->dev, ret, "Failed to add counter\n");  in intel_qep_probe()
448 	struct device *dev = &pci->dev;  in intel_qep_remove()
451 	if (!qep->enabled)  in intel_qep_remove()
462 	qep->qepcon = intel_qep_readl(qep, INTEL_QEPCON);  in intel_qep_suspend()
463 	qep->qepflt = intel_qep_readl(qep, INTEL_QEPFLT);  in intel_qep_suspend()
464 	qep->qepmax = intel_qep_readl(qep, INTEL_QEPMAX);  in intel_qep_suspend()
482 	intel_qep_writel(qep, INTEL_QEPFLT, qep->qepflt);  in intel_qep_resume()
483 	intel_qep_writel(qep, INTEL_QEPMAX, qep->qepmax);  in intel_qep_resume()
487 	intel_qep_writel(qep, INTEL_QEPCON, qep->qepcon & ~INTEL_QEPCON_EN);  in intel_qep_resume()
491 	intel_qep_writel(qep, INTEL_QEPCON, qep->qepcon);  in intel_qep_resume()
510 	.name = "intel-qep",
526 MODULE_IMPORT_NS(COUNTER);