Lines Matching +full:assert +full:- +full:falling +full:- +full:edge
1 // SPDX-License-Identifier: GPL-2.0+
3 * Hardware driver for DAQ-STC based boards
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 * Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
17 * 340747b.pdf AT-MIO E series Register Level Programmer Manual
19 * 340934b.pdf DAQ-STC reference manual
31 * 321791a.pdf discontinuation of at-mio-16e-10 rev. c
32 * 321808a.pdf about at-mio-16e-10 rev P
33 * 321837a.pdf discontinuation of at-mio-16de-10 rev d
34 * 321838a.pdf about at-mio-16de-10 rev N
37 * - the interrupt routine needs to be cleaned up
39 * 2006-02-07: S-Series PCI-6143: Support has been added but is not
173 RANGE_ext(-1, 1),
232 writel(data, dev->mmio + reg); in ni_writel()
237 writew(data, dev->mmio + reg); in ni_writew()
242 writeb(data, dev->mmio + reg); in ni_writeb()
247 return readl(dev->mmio + reg); in ni_readl()
252 return readw(dev->mmio + reg); in ni_readw()
257 return readb(dev->mmio + reg); in ni_readb()
264 outl(data, dev->iobase + reg); in ni_writel()
269 outw(data, dev->iobase + reg); in ni_writew()
274 outb(data, dev->iobase + reg); in ni_writeb()
279 return inl(dev->iobase + reg); in ni_readl()
284 return inw(dev->iobase + reg); in ni_readw()
289 return inb(dev->iobase + reg); in ni_readb()
298 * The AT-MIO and DAQCard devices map the low 8 STC registers to
302 * 611x devices map the read registers to iobase+(addr-1)*2.
303 * For now non-windowed STC access is disabled if a PCIMIO device
304 * is detected (devpriv->mite has been initialized).
371 [NISTC_INTA2_ENA_REG] = { 0, 0 }, /* E-Series only */
373 [NISTC_INTB2_ENA_REG] = { 0, 0 }, /* E-Series only */
395 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n", in m_series_stc_write()
400 switch (regmap->size) { in m_series_stc_write()
402 ni_writel(dev, data, regmap->mio_reg); in m_series_stc_write()
405 ni_writew(dev, data, regmap->mio_reg); in m_series_stc_write()
408 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n", in m_series_stc_write()
443 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n", in m_series_stc_read()
448 switch (regmap->size) { in m_series_stc_read()
450 return ni_readl(dev, regmap->mio_reg); in m_series_stc_read()
452 return ni_readw(dev, regmap->mio_reg); in m_series_stc_read()
454 return ni_readb(dev, regmap->mio_reg); in m_series_stc_read()
456 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n", in m_series_stc_read()
465 struct ni_private *devpriv = dev->private; in ni_stc_writew()
468 if (devpriv->is_m_series) { in ni_stc_writew()
471 spin_lock_irqsave(&devpriv->window_lock, flags); in ni_stc_writew()
472 if (!devpriv->mite && reg < 8) { in ni_stc_writew()
478 spin_unlock_irqrestore(&devpriv->window_lock, flags); in ni_stc_writew()
485 struct ni_private *devpriv = dev->private; in ni_stc_writel()
487 if (devpriv->is_m_series) { in ni_stc_writel()
497 struct ni_private *devpriv = dev->private; in ni_stc_readw()
501 if (devpriv->is_m_series) { in ni_stc_readw()
504 spin_lock_irqsave(&devpriv->window_lock, flags); in ni_stc_readw()
505 if (!devpriv->mite && reg < 8) { in ni_stc_readw()
511 spin_unlock_irqrestore(&devpriv->window_lock, flags); in ni_stc_readw()
518 struct ni_private *devpriv = dev->private; in ni_stc_readl()
521 if (devpriv->is_m_series) { in ni_stc_readl()
534 struct ni_private *devpriv = dev->private; in ni_set_bitfield()
537 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); in ni_set_bitfield()
540 devpriv->int_a_enable_reg &= ~bit_mask; in ni_set_bitfield()
541 devpriv->int_a_enable_reg |= bit_values & bit_mask; in ni_set_bitfield()
542 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg); in ni_set_bitfield()
545 devpriv->int_b_enable_reg &= ~bit_mask; in ni_set_bitfield()
546 devpriv->int_b_enable_reg |= bit_values & bit_mask; in ni_set_bitfield()
547 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg); in ni_set_bitfield()
550 devpriv->io_bidirection_pin_reg &= ~bit_mask; in ni_set_bitfield()
551 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask; in ni_set_bitfield()
552 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg); in ni_set_bitfield()
555 devpriv->ai_ao_select_reg &= ~bit_mask; in ni_set_bitfield()
556 devpriv->ai_ao_select_reg |= bit_values & bit_mask; in ni_set_bitfield()
557 ni_writeb(dev, devpriv->ai_ao_select_reg, reg); in ni_set_bitfield()
560 devpriv->g0_g1_select_reg &= ~bit_mask; in ni_set_bitfield()
561 devpriv->g0_g1_select_reg |= bit_values & bit_mask; in ni_set_bitfield()
562 ni_writeb(dev, devpriv->g0_g1_select_reg, reg); in ni_set_bitfield()
565 devpriv->cdio_dma_select_reg &= ~bit_mask; in ni_set_bitfield()
566 devpriv->cdio_dma_select_reg |= bit_values & bit_mask; in ni_set_bitfield()
567 ni_writeb(dev, devpriv->cdio_dma_select_reg, reg); in ni_set_bitfield()
570 dev_err(dev->class_dev, "called with invalid register %d\n", in ni_set_bitfield()
574 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); in ni_set_bitfield()
587 struct ni_private *devpriv = dev->private; in ni_request_ai_mite_channel()
592 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_request_ai_mite_channel()
593 mite_chan = mite_request_channel(devpriv->mite, devpriv->ai_mite_ring); in ni_request_ai_mite_channel()
595 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_ai_mite_channel()
596 dev_err(dev->class_dev, in ni_request_ai_mite_channel()
598 return -EBUSY; in ni_request_ai_mite_channel()
600 mite_chan->dir = COMEDI_INPUT; in ni_request_ai_mite_channel()
601 devpriv->ai_mite_chan = mite_chan; in ni_request_ai_mite_channel()
603 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel); in ni_request_ai_mite_channel()
607 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_ai_mite_channel()
613 struct ni_private *devpriv = dev->private; in ni_request_ao_mite_channel()
618 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_request_ao_mite_channel()
619 mite_chan = mite_request_channel(devpriv->mite, devpriv->ao_mite_ring); in ni_request_ao_mite_channel()
621 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_ao_mite_channel()
622 dev_err(dev->class_dev, in ni_request_ao_mite_channel()
624 return -EBUSY; in ni_request_ao_mite_channel()
626 mite_chan->dir = COMEDI_OUTPUT; in ni_request_ao_mite_channel()
627 devpriv->ao_mite_chan = mite_chan; in ni_request_ao_mite_channel()
629 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel); in ni_request_ao_mite_channel()
633 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_ao_mite_channel()
641 struct ni_private *devpriv = dev->private; in ni_request_gpct_mite_channel()
642 struct ni_gpct *counter = &devpriv->counter_dev->counters[gpct_index]; in ni_request_gpct_mite_channel()
647 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_request_gpct_mite_channel()
648 mite_chan = mite_request_channel(devpriv->mite, in ni_request_gpct_mite_channel()
649 devpriv->gpct_mite_ring[gpct_index]); in ni_request_gpct_mite_channel()
651 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_gpct_mite_channel()
652 dev_err(dev->class_dev, in ni_request_gpct_mite_channel()
654 return -EBUSY; in ni_request_gpct_mite_channel()
656 mite_chan->dir = direction; in ni_request_gpct_mite_channel()
659 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel); in ni_request_gpct_mite_channel()
664 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_gpct_mite_channel()
670 struct ni_private *devpriv = dev->private; in ni_request_cdo_mite_channel()
675 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_request_cdo_mite_channel()
676 mite_chan = mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring); in ni_request_cdo_mite_channel()
678 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_cdo_mite_channel()
679 dev_err(dev->class_dev, in ni_request_cdo_mite_channel()
681 return -EBUSY; in ni_request_cdo_mite_channel()
683 mite_chan->dir = COMEDI_OUTPUT; in ni_request_cdo_mite_channel()
684 devpriv->cdo_mite_chan = mite_chan; in ni_request_cdo_mite_channel()
692 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel); in ni_request_cdo_mite_channel()
697 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_cdo_mite_channel()
705 struct ni_private *devpriv = dev->private; in ni_release_ai_mite_channel()
708 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_release_ai_mite_channel()
709 if (devpriv->ai_mite_chan) { in ni_release_ai_mite_channel()
712 mite_release_channel(devpriv->ai_mite_chan); in ni_release_ai_mite_channel()
713 devpriv->ai_mite_chan = NULL; in ni_release_ai_mite_channel()
715 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_release_ai_mite_channel()
722 struct ni_private *devpriv = dev->private; in ni_release_ao_mite_channel()
725 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_release_ao_mite_channel()
726 if (devpriv->ao_mite_chan) { in ni_release_ao_mite_channel()
729 mite_release_channel(devpriv->ao_mite_chan); in ni_release_ao_mite_channel()
730 devpriv->ao_mite_chan = NULL; in ni_release_ao_mite_channel()
732 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_release_ao_mite_channel()
740 struct ni_private *devpriv = dev->private; in ni_release_gpct_mite_channel()
743 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_release_gpct_mite_channel()
744 if (devpriv->counter_dev->counters[gpct_index].mite_chan) { in ni_release_gpct_mite_channel()
746 devpriv->counter_dev->counters[gpct_index].mite_chan; in ni_release_gpct_mite_channel()
750 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index], in ni_release_gpct_mite_channel()
754 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_release_gpct_mite_channel()
759 struct ni_private *devpriv = dev->private; in ni_release_cdo_mite_channel()
762 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_release_cdo_mite_channel()
763 if (devpriv->cdo_mite_chan) { in ni_release_cdo_mite_channel()
766 mite_release_channel(devpriv->cdo_mite_chan); in ni_release_cdo_mite_channel()
767 devpriv->cdo_mite_chan = NULL; in ni_release_cdo_mite_channel()
769 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_release_cdo_mite_channel()
775 struct ni_private *devpriv = dev->private; in ni_e_series_enable_second_irq()
779 if (devpriv->is_m_series || gpct_index > 1) in ni_e_series_enable_second_irq()
783 * e-series boards use the second irq signals to generate in ni_e_series_enable_second_irq()
801 struct ni_private *devpriv = dev->private; in ni_clear_ai_fifo()
805 if (devpriv->is_6143) { in ni_clear_ai_fifo()
816 dev_err(dev->class_dev, "FIFO flush timeout\n"); in ni_clear_ai_fifo()
819 if (devpriv->is_625x) { in ni_clear_ai_fifo()
841 struct ni_private *devpriv = dev->private; in ni_ao_win_outw()
844 spin_lock_irqsave(&devpriv->window_lock, flags); in ni_ao_win_outw()
847 spin_unlock_irqrestore(&devpriv->window_lock, flags); in ni_ao_win_outw()
853 struct ni_private *devpriv = dev->private; in ni_ao_win_outl()
856 spin_lock_irqsave(&devpriv->window_lock, flags); in ni_ao_win_outl()
859 spin_unlock_irqrestore(&devpriv->window_lock, flags); in ni_ao_win_outl()
864 struct ni_private *devpriv = dev->private; in ni_ao_win_inw()
868 spin_lock_irqsave(&devpriv->window_lock, flags); in ni_ao_win_inw()
871 spin_unlock_irqrestore(&devpriv->window_lock, flags); in ni_ao_win_inw()
881 * so this is actually quite fast--- If you must wrap another function around
901 struct ni_private *devpriv = dev->private; in ni_sync_ai_dma()
902 struct comedi_subdevice *s = dev->read_subdev; in ni_sync_ai_dma()
905 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_sync_ai_dma()
906 if (devpriv->ai_mite_chan) in ni_sync_ai_dma()
907 mite_sync_dma(devpriv->ai_mite_chan, s); in ni_sync_ai_dma()
908 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_sync_ai_dma()
913 struct ni_private *devpriv = dev->private; in ni_ai_drain_dma()
919 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_ai_drain_dma()
920 if (devpriv->ai_mite_chan) { in ni_ai_drain_dma()
924 mite_bytes_in_transit(devpriv->ai_mite_chan) == 0) in ni_ai_drain_dma()
929 dev_err(dev->class_dev, "timed out\n"); in ni_ai_drain_dma()
930 dev_err(dev->class_dev, in ni_ai_drain_dma()
932 mite_bytes_in_transit(devpriv->ai_mite_chan), in ni_ai_drain_dma()
934 retval = -1; in ni_ai_drain_dma()
937 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_ai_drain_dma()
962 dev_err(dev->class_dev, "timed out waiting for dma load\n"); in ni_ao_wait_for_dma_load()
963 return -EPIPE; in ni_ao_wait_for_dma_load()
974 struct ni_private *devpriv = dev->private; in ni_ao_fifo_load()
982 if (devpriv->is_6xxx) { in ni_ao_fifo_load()
985 if (!devpriv->is_6711) { in ni_ao_fifo_load()
1002 * IRQ is in edge mode, we never get another interrupt, because
1016 const struct ni_board_struct *board = dev->board_ptr; in ni_ao_fifo_half_empty()
1022 s->async->events |= COMEDI_CB_OVERFLOW; in ni_ao_fifo_half_empty()
1027 if (nsamples > board->ao_fifo_depth / 2) in ni_ao_fifo_half_empty()
1028 nsamples = board->ao_fifo_depth / 2; in ni_ao_fifo_half_empty()
1038 const struct ni_board_struct *board = dev->board_ptr; in ni_ao_prep_fifo()
1039 struct ni_private *devpriv = dev->private; in ni_ao_prep_fifo()
1045 if (devpriv->is_6xxx) in ni_ao_prep_fifo()
1054 if (nsamples > board->ao_fifo_depth) in ni_ao_prep_fifo()
1055 nsamples = board->ao_fifo_depth; in ni_ao_prep_fifo()
1065 struct ni_private *devpriv = dev->private; in ni_ai_fifo_read()
1066 struct comedi_async *async = s->async; in ni_ai_fifo_read()
1071 if (devpriv->is_611x) { in ni_ai_fifo_read()
1086 } else if (devpriv->is_6143) { in ni_ai_fifo_read()
1108 if (n > ARRAY_SIZE(devpriv->ai_fifo_buffer)) { in ni_ai_fifo_read()
1109 dev_err(dev->class_dev, in ni_ai_fifo_read()
1111 async->events |= COMEDI_CB_ERROR; in ni_ai_fifo_read()
1115 devpriv->ai_fifo_buffer[i] = in ni_ai_fifo_read()
1118 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n); in ni_ai_fifo_read()
1124 const struct ni_board_struct *board = dev->board_ptr; in ni_handle_fifo_half_full()
1125 struct comedi_subdevice *s = dev->read_subdev; in ni_handle_fifo_half_full()
1128 n = board->ai_fifo_depth / 2; in ni_handle_fifo_half_full()
1137 struct ni_private *devpriv = dev->private; in ni_handle_fifo_dregs()
1138 struct comedi_subdevice *s = dev->read_subdev; in ni_handle_fifo_dregs()
1143 if (devpriv->is_611x) { in ni_handle_fifo_dregs()
1154 } else if (devpriv->is_6143) { in ni_handle_fifo_dregs()
1182 i < ARRAY_SIZE(devpriv->ai_fifo_buffer); i++) { in ni_handle_fifo_dregs()
1187 devpriv->ai_fifo_buffer[i] = in ni_handle_fifo_dregs()
1190 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i); in ni_handle_fifo_dregs()
1197 struct ni_private *devpriv = dev->private; in get_last_sample_611x()
1198 struct comedi_subdevice *s = dev->read_subdev; in get_last_sample_611x()
1202 if (!devpriv->is_611x) in get_last_sample_611x()
1215 struct ni_private *devpriv = dev->private; in get_last_sample_6143()
1216 struct comedi_subdevice *s = dev->read_subdev; in get_last_sample_6143()
1220 if (!devpriv->is_6143) in get_last_sample_6143()
1237 struct comedi_subdevice *s = dev->read_subdev; in shutdown_ai_command()
1246 s->async->events |= COMEDI_CB_EOA; in shutdown_ai_command()
1251 struct ni_private *devpriv = dev->private; in ni_handle_eos()
1253 if (devpriv->aimode == AIMODE_SCAN) { in ni_handle_eos()
1260 if ((s->async->events & COMEDI_CB_EOS)) in ni_handle_eos()
1266 s->async->events |= COMEDI_CB_EOS; in ni_handle_eos()
1270 if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS) in ni_handle_eos()
1278 struct ni_private *devpriv = dev->private; in handle_gpct_interrupt()
1281 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)]; in handle_gpct_interrupt()
1283 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index], in handle_gpct_interrupt()
1311 struct comedi_cmd *cmd = &s->async->cmd; in handle_a_interrupt()
1317 dev_err(dev->class_dev, "Card removed?\n"); in handle_a_interrupt()
1323 s->async->events |= COMEDI_CB_ERROR; in handle_a_interrupt()
1327 dev_err(dev->class_dev, "ai error a_status=%04x\n", in handle_a_interrupt()
1332 s->async->events |= COMEDI_CB_ERROR; in handle_a_interrupt()
1334 s->async->events |= COMEDI_CB_OVERFLOW; in handle_a_interrupt()
1338 if (cmd->stop_src == TRIG_COUNT) in handle_a_interrupt()
1393 dev_err(dev->class_dev, in handle_b_interrupt()
1396 s->async->events |= COMEDI_CB_OVERFLOW; in handle_b_interrupt()
1399 if (s->async->cmd.stop_src != TRIG_NONE && in handle_b_interrupt()
1401 s->async->events |= COMEDI_CB_EOA; in handle_b_interrupt()
1409 dev_err(dev->class_dev, "AO buffer underrun\n"); in handle_b_interrupt()
1413 s->async->events |= COMEDI_CB_OVERFLOW; in handle_b_interrupt()
1423 struct ni_private *devpriv = dev->private; in ni_ai_munge()
1424 struct comedi_async *async = s->async; in ni_ai_munge()
1425 struct comedi_cmd *cmd = &async->cmd; in ni_ai_munge()
1437 if (s->subdev_flags & SDF_LSAMPL) in ni_ai_munge()
1442 if (s->subdev_flags & SDF_LSAMPL) in ni_ai_munge()
1443 larray[i] += devpriv->ai_offset[chan_index]; in ni_ai_munge()
1445 array[i] += devpriv->ai_offset[chan_index]; in ni_ai_munge()
1447 chan_index %= cmd->chanlist_len; in ni_ai_munge()
1455 struct ni_private *devpriv = dev->private; in ni_ai_setup_MITE_dma()
1456 struct comedi_subdevice *s = dev->read_subdev; in ni_ai_setup_MITE_dma()
1465 comedi_buf_write_alloc(s, s->async->prealloc_bufsz); in ni_ai_setup_MITE_dma()
1467 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_ai_setup_MITE_dma()
1468 if (!devpriv->ai_mite_chan) { in ni_ai_setup_MITE_dma()
1469 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_ai_setup_MITE_dma()
1470 return -EIO; in ni_ai_setup_MITE_dma()
1473 if (devpriv->is_611x || devpriv->is_6143) in ni_ai_setup_MITE_dma()
1474 mite_prep_dma(devpriv->ai_mite_chan, 32, 16); in ni_ai_setup_MITE_dma()
1475 else if (devpriv->is_628x) in ni_ai_setup_MITE_dma()
1476 mite_prep_dma(devpriv->ai_mite_chan, 32, 32); in ni_ai_setup_MITE_dma()
1478 mite_prep_dma(devpriv->ai_mite_chan, 16, 16); in ni_ai_setup_MITE_dma()
1481 mite_dma_arm(devpriv->ai_mite_chan); in ni_ai_setup_MITE_dma()
1482 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_ai_setup_MITE_dma()
1489 struct ni_private *devpriv = dev->private; in ni_ao_setup_MITE_dma()
1490 struct comedi_subdevice *s = dev->write_subdev; in ni_ao_setup_MITE_dma()
1499 comedi_buf_read_alloc(s, s->async->prealloc_bufsz); in ni_ao_setup_MITE_dma()
1501 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_ao_setup_MITE_dma()
1502 if (devpriv->ao_mite_chan) { in ni_ao_setup_MITE_dma()
1503 if (devpriv->is_611x || devpriv->is_6713) { in ni_ao_setup_MITE_dma()
1504 mite_prep_dma(devpriv->ao_mite_chan, 32, 32); in ni_ao_setup_MITE_dma()
1511 mite_prep_dma(devpriv->ao_mite_chan, 16, 32); in ni_ao_setup_MITE_dma()
1513 mite_dma_arm(devpriv->ao_mite_chan); in ni_ao_setup_MITE_dma()
1515 retval = -EIO; in ni_ao_setup_MITE_dma()
1517 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_ao_setup_MITE_dma()
1531 struct ni_private *devpriv = dev->private; in ni_ai_reset()
1544 if (!devpriv->is_6143) in ni_ai_reset()
1553 /* generate FIFO interrupts on non-empty */ in ni_ai_reset()
1564 if (devpriv->is_611x) { in ni_ai_reset()
1566 } else if (devpriv->is_6143) { in ni_ai_reset()
1570 if (devpriv->is_622x) in ni_ai_reset()
1601 spin_lock_irqsave(&dev->spinlock, flags); in ni_ai_poll()
1608 spin_unlock_irqrestore(&dev->spinlock, flags); in ni_ai_poll()
1626 dev_err(dev->class_dev, "timeout loading channel/gain list\n"); in ni_prime_channelgain_list()
1633 const struct ni_board_struct *board = dev->board_ptr; in ni_m_series_load_channelgain_list()
1634 struct ni_private *devpriv = dev->private; in ni_m_series_load_channelgain_list()
1647 range_code = ni_gainlkup[board->gainlkup][range]; in ni_m_series_load_channelgain_list()
1652 devpriv->ai_calib_source; in ni_m_series_load_channelgain_list()
1669 range_code = ni_gainlkup[board->gainlkup][range]; in ni_m_series_load_channelgain_list()
1670 devpriv->ai_offset[i] = 0; in ni_m_series_load_channelgain_list()
1687 if (i == n_chan - 1) in ni_m_series_load_channelgain_list()
1705 * bits 15-9: same
1707 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
1708 * 1001 gain=0.1 (+/- 50)
1718 * bits 12-14: Channel Type
1724 * bits 0-2: channel
1725 * valid channels are 0-3
1731 const struct ni_board_struct *board = dev->board_ptr; in ni_load_channelgain_list()
1732 struct ni_private *devpriv = dev->private; in ni_load_channelgain_list()
1733 unsigned int offset = (s->maxdata + 1) >> 1; in ni_load_channelgain_list()
1739 if (devpriv->is_m_series) { in ni_load_channelgain_list()
1743 if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) { in ni_load_channelgain_list()
1744 if (devpriv->changain_state && in ni_load_channelgain_list()
1745 devpriv->changain_spec == list[0]) { in ni_load_channelgain_list()
1749 devpriv->changain_state = 1; in ni_load_channelgain_list()
1750 devpriv->changain_spec = list[0]; in ni_load_channelgain_list()
1752 devpriv->changain_state = 0; in ni_load_channelgain_list()
1758 if (devpriv->is_6143) { in ni_load_channelgain_list()
1760 !devpriv->ai_calib_source_enabled) { in ni_load_channelgain_list()
1762 ni_writew(dev, devpriv->ai_calib_source | in ni_load_channelgain_list()
1765 ni_writew(dev, devpriv->ai_calib_source, in ni_load_channelgain_list()
1767 devpriv->ai_calib_source_enabled = 1; in ni_load_channelgain_list()
1771 devpriv->ai_calib_source_enabled) { in ni_load_channelgain_list()
1773 ni_writew(dev, devpriv->ai_calib_source | in ni_load_channelgain_list()
1776 ni_writew(dev, devpriv->ai_calib_source, in ni_load_channelgain_list()
1778 devpriv->ai_calib_source_enabled = 0; in ni_load_channelgain_list()
1785 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE)) in ni_load_channelgain_list()
1786 chan = devpriv->ai_calib_source; in ni_load_channelgain_list()
1794 range = ni_gainlkup[board->gainlkup][range]; in ni_load_channelgain_list()
1795 if (devpriv->is_611x) in ni_load_channelgain_list()
1796 devpriv->ai_offset[i] = offset; in ni_load_channelgain_list()
1798 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset; in ni_load_channelgain_list()
1802 if (devpriv->is_611x) in ni_load_channelgain_list()
1806 if (devpriv->is_611x) in ni_load_channelgain_list()
1808 else if (devpriv->is_6143) in ni_load_channelgain_list()
1828 if (!devpriv->is_6143) { in ni_load_channelgain_list()
1831 if (i == n_chan - 1) in ni_load_channelgain_list()
1841 if (!devpriv->is_611x && !devpriv->is_6143) in ni_load_channelgain_list()
1850 struct ni_private *devpriv = dev->private; in ni_ai_insn_read()
1851 unsigned int mask = s->maxdata; in ni_ai_insn_read()
1856 ni_load_channelgain_list(dev, s, 1, &insn->chanspec); in ni_ai_insn_read()
1860 signbits = devpriv->ai_offset[0]; in ni_ai_insn_read()
1861 if (devpriv->is_611x) { in ni_ai_insn_read()
1867 for (n = 0; n < insn->n; n++) { in ni_ai_insn_read()
1870 /* The 611x has screwy 32-bit FIFOs. */ in ni_ai_insn_read()
1889 dev_err(dev->class_dev, "timeout\n"); in ni_ai_insn_read()
1890 return -ETIME; in ni_ai_insn_read()
1895 } else if (devpriv->is_6143) { in ni_ai_insn_read()
1896 for (n = 0; n < insn->n; n++) { in ni_ai_insn_read()
1901 * The 6143 has 32-bit FIFOs. You need to strobe a in ni_ai_insn_read()
1918 dev_err(dev->class_dev, "timeout\n"); in ni_ai_insn_read()
1919 return -ETIME; in ni_ai_insn_read()
1924 for (n = 0; n < insn->n; n++) { in ni_ai_insn_read()
1933 dev_err(dev->class_dev, "timeout\n"); in ni_ai_insn_read()
1934 return -ETIME; in ni_ai_insn_read()
1936 if (devpriv->is_m_series) { in ni_ai_insn_read()
1947 return insn->n; in ni_ai_insn_read()
1953 struct ni_private *devpriv = dev->private; in ni_ns_to_timer()
1959 divider = DIV_ROUND_CLOSEST(nanosec, devpriv->clock_ns); in ni_ns_to_timer()
1962 divider = (nanosec) / devpriv->clock_ns; in ni_ns_to_timer()
1965 divider = DIV_ROUND_UP(nanosec, devpriv->clock_ns); in ni_ns_to_timer()
1968 return divider - 1; in ni_ns_to_timer()
1973 struct ni_private *devpriv = dev->private; in ni_timer_to_ns()
1975 return devpriv->clock_ns * (timer + 1); in ni_timer_to_ns()
1986 if (cmd->stop_arg > 0 && cmd->stop_arg < max_count) in ni_cmd_set_mite_transfer()
1987 nbytes = cmd->stop_arg; in ni_cmd_set_mite_transfer()
1990 if (nbytes > sdev->async->prealloc_bufsz) { in ni_cmd_set_mite_transfer()
1991 if (cmd->stop_arg > 0) in ni_cmd_set_mite_transfer()
1992 dev_err(sdev->device->class_dev, in ni_cmd_set_mite_transfer()
2001 nbytes = sdev->async->prealloc_bufsz; in ni_cmd_set_mite_transfer()
2006 dev_err(sdev->device->class_dev, in ni_cmd_set_mite_transfer()
2015 const struct ni_board_struct *board = dev->board_ptr; in ni_min_ai_scan_period_ns()
2016 struct ni_private *devpriv = dev->private; in ni_min_ai_scan_period_ns()
2018 /* simultaneously-sampled inputs */ in ni_min_ai_scan_period_ns()
2019 if (devpriv->is_611x || devpriv->is_6143) in ni_min_ai_scan_period_ns()
2020 return board->ai_speed; in ni_min_ai_scan_period_ns()
2023 return board->ai_speed * num_channels; in ni_min_ai_scan_period_ns()
2029 const struct ni_board_struct *board = dev->board_ptr; in ni_ai_cmdtest()
2030 struct ni_private *devpriv = dev->private; in ni_ai_cmdtest()
2036 err |= comedi_check_trigger_src(&cmd->start_src, in ni_ai_cmdtest()
2038 err |= comedi_check_trigger_src(&cmd->scan_begin_src, in ni_ai_cmdtest()
2042 if (devpriv->is_611x || devpriv->is_6143) in ni_ai_cmdtest()
2044 err |= comedi_check_trigger_src(&cmd->convert_src, sources); in ni_ai_cmdtest()
2046 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); in ni_ai_cmdtest()
2047 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); in ni_ai_cmdtest()
2054 err |= comedi_check_trigger_is_unique(cmd->start_src); in ni_ai_cmdtest()
2055 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src); in ni_ai_cmdtest()
2056 err |= comedi_check_trigger_is_unique(cmd->convert_src); in ni_ai_cmdtest()
2057 err |= comedi_check_trigger_is_unique(cmd->stop_src); in ni_ai_cmdtest()
2066 switch (cmd->start_src) { in ni_ai_cmdtest()
2069 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); in ni_ai_cmdtest()
2072 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->start_arg), in ni_ai_cmdtest()
2074 &devpriv->routing_tables, 1); in ni_ai_cmdtest()
2078 if (cmd->scan_begin_src == TRIG_TIMER) { in ni_ai_cmdtest()
2079 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg, in ni_ai_cmdtest()
2080 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len)); in ni_ai_cmdtest()
2081 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, in ni_ai_cmdtest()
2082 devpriv->clock_ns * in ni_ai_cmdtest()
2084 } else if (cmd->scan_begin_src == TRIG_EXT) { in ni_ai_cmdtest()
2086 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->scan_begin_arg), in ni_ai_cmdtest()
2088 &devpriv->routing_tables, 1); in ni_ai_cmdtest()
2090 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0); in ni_ai_cmdtest()
2093 if (cmd->convert_src == TRIG_TIMER) { in ni_ai_cmdtest()
2094 if (devpriv->is_611x || devpriv->is_6143) { in ni_ai_cmdtest()
2095 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, in ni_ai_cmdtest()
2098 err |= comedi_check_trigger_arg_min(&cmd->convert_arg, in ni_ai_cmdtest()
2099 board->ai_speed); in ni_ai_cmdtest()
2100 err |= comedi_check_trigger_arg_max(&cmd->convert_arg, in ni_ai_cmdtest()
2101 devpriv->clock_ns * in ni_ai_cmdtest()
2104 } else if (cmd->convert_src == TRIG_EXT) { in ni_ai_cmdtest()
2106 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->convert_arg), in ni_ai_cmdtest()
2108 &devpriv->routing_tables, 1); in ni_ai_cmdtest()
2109 } else if (cmd->convert_src == TRIG_NOW) { in ni_ai_cmdtest()
2110 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0); in ni_ai_cmdtest()
2113 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, in ni_ai_cmdtest()
2114 cmd->chanlist_len); in ni_ai_cmdtest()
2116 if (cmd->stop_src == TRIG_COUNT) { in ni_ai_cmdtest()
2119 if (devpriv->is_611x) in ni_ai_cmdtest()
2120 max_count -= num_adc_stages_611x; in ni_ai_cmdtest()
2121 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count); in ni_ai_cmdtest()
2122 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1); in ni_ai_cmdtest()
2125 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0); in ni_ai_cmdtest()
2133 if (cmd->scan_begin_src == TRIG_TIMER) { in ni_ai_cmdtest()
2134 unsigned int tmp = cmd->scan_begin_arg; in ni_ai_cmdtest()
2136 cmd->scan_begin_arg = in ni_ai_cmdtest()
2138 cmd->scan_begin_arg, in ni_ai_cmdtest()
2139 cmd->flags)); in ni_ai_cmdtest()
2140 if (tmp != cmd->scan_begin_arg) in ni_ai_cmdtest()
2143 if (cmd->convert_src == TRIG_TIMER) { in ni_ai_cmdtest()
2144 if (!devpriv->is_611x && !devpriv->is_6143) { in ni_ai_cmdtest()
2145 unsigned int tmp = cmd->convert_arg; in ni_ai_cmdtest()
2147 cmd->convert_arg = in ni_ai_cmdtest()
2149 cmd->convert_arg, in ni_ai_cmdtest()
2150 cmd->flags)); in ni_ai_cmdtest()
2151 if (tmp != cmd->convert_arg) in ni_ai_cmdtest()
2153 if (cmd->scan_begin_src == TRIG_TIMER && in ni_ai_cmdtest()
2154 cmd->scan_begin_arg < in ni_ai_cmdtest()
2155 cmd->convert_arg * cmd->scan_end_arg) { in ni_ai_cmdtest()
2156 cmd->scan_begin_arg = in ni_ai_cmdtest()
2157 cmd->convert_arg * cmd->scan_end_arg; in ni_ai_cmdtest()
2173 struct ni_private *devpriv = dev->private; in ni_ai_inttrig()
2174 struct comedi_cmd *cmd = &s->async->cmd; in ni_ai_inttrig()
2176 if (trig_num != cmd->start_arg) in ni_ai_inttrig()
2177 return -EINVAL; in ni_ai_inttrig()
2179 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2, in ni_ai_inttrig()
2181 s->async->inttrig = NULL; in ni_ai_inttrig()
2188 struct ni_private *devpriv = dev->private; in ni_ai_cmd()
2189 const struct comedi_cmd *cmd = &s->async->cmd; in ni_ai_cmd()
2198 if (dev->irq == 0) { in ni_ai_cmd()
2199 dev_err(dev->class_dev, "cannot run command without an irq\n"); in ni_ai_cmd()
2200 return -EIO; in ni_ai_cmd()
2204 ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist); in ni_ai_cmd()
2213 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA; in ni_ai_cmd()
2214 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG); in ni_ai_cmd()
2217 switch (cmd->start_src) { in ni_ai_cmd()
2226 CR_CHAN(cmd->start_arg), in ni_ai_cmd()
2228 &devpriv->routing_tables, 1)); in ni_ai_cmd()
2230 if (cmd->start_arg & CR_INVERT) in ni_ai_cmd()
2232 if (cmd->start_arg & CR_EDGE) in ni_ai_cmd()
2243 if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) { in ni_ai_cmd()
2254 devpriv->ai_cmd2 = 0; in ni_ai_cmd()
2255 switch (cmd->stop_src) { in ni_ai_cmd()
2257 stop_count = cmd->stop_arg - 1; in ni_ai_cmd()
2259 if (devpriv->is_611x) { in ni_ai_cmd()
2274 devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS; in ni_ai_cmd()
2280 if (cmd->chanlist_len > 1) in ni_ai_cmd()
2299 switch (cmd->scan_begin_src) { in ni_ai_cmd()
2306 * NISTC_AI_START_POLARITY=0 (?) rising edge in ni_ai_cmd()
2307 * NISTC_AI_START_EDGE=1 edge triggered in ni_ai_cmd()
2310 * NISTC_AI_STOP_POLARITY=0 rising edge in ni_ai_cmd()
2324 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg, in ni_ai_cmd()
2330 if (cmd->scan_begin_arg & CR_EDGE) in ni_ai_cmd()
2332 if (cmd->scan_begin_arg & CR_INVERT) /* falling edge */ in ni_ai_cmd()
2334 if (cmd->scan_begin_src != cmd->convert_src || in ni_ai_cmd()
2335 (cmd->scan_begin_arg & ~CR_EDGE) != in ni_ai_cmd()
2336 (cmd->convert_arg & ~CR_EDGE)) in ni_ai_cmd()
2341 CR_CHAN(cmd->scan_begin_arg), in ni_ai_cmd()
2343 &devpriv->routing_tables, 1)); in ni_ai_cmd()
2348 switch (cmd->convert_src) { in ni_ai_cmd()
2351 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW) in ni_ai_cmd()
2354 timer = ni_ns_to_timer(dev, cmd->convert_arg, in ni_ai_cmd()
2373 CR_CHAN(cmd->convert_arg), in ni_ai_cmd()
2375 &devpriv->routing_tables, 1)); in ni_ai_cmd()
2376 if ((cmd->convert_arg & CR_INVERT) == 0) in ni_ai_cmd()
2387 if (dev->irq) { in ni_ai_cmd()
2396 if ((cmd->flags & CMDF_WAKE_EOS) || in ni_ai_cmd()
2397 (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) { in ni_ai_cmd()
2398 /* wake on end-of-scan */ in ni_ai_cmd()
2399 devpriv->aimode = AIMODE_SCAN; in ni_ai_cmd()
2401 devpriv->aimode = AIMODE_HALF_FULL; in ni_ai_cmd()
2404 switch (devpriv->aimode) { in ni_ai_cmd()
2406 /* FIFO interrupts and DMA requests on half-full */ in ni_ai_cmd()
2416 /* generate FIFO interrupts on non-empty */ in ni_ai_cmd()
2448 switch (cmd->scan_begin_src) { in ni_ai_cmd()
2474 if (cmd->start_src == TRIG_NOW) { in ni_ai_cmd()
2476 devpriv->ai_cmd2, in ni_ai_cmd()
2478 s->async->inttrig = NULL; in ni_ai_cmd()
2479 } else if (cmd->start_src == TRIG_EXT) { in ni_ai_cmd()
2480 s->async->inttrig = NULL; in ni_ai_cmd()
2482 s->async->inttrig = ni_ai_inttrig; in ni_ai_cmd()
2492 const struct ni_board_struct *board = dev->board_ptr; in ni_ai_insn_config()
2493 struct ni_private *devpriv = dev->private; in ni_ai_insn_config()
2495 if (insn->n < 1) in ni_ai_insn_config()
2496 return -EINVAL; in ni_ai_insn_config()
2500 if (devpriv->is_m_series) { in ni_ai_insn_config()
2502 return -EINVAL; in ni_ai_insn_config()
2503 devpriv->ai_calib_source = data[1]; in ni_ai_insn_config()
2504 } else if (devpriv->is_6143) { in ni_ai_insn_config()
2509 devpriv->ai_calib_source = calib_source; in ni_ai_insn_config()
2519 return -EINVAL; in ni_ai_insn_config()
2520 devpriv->ai_calib_source = calib_source; in ni_ai_insn_config()
2521 if (devpriv->is_611x) { in ni_ai_insn_config()
2531 if (devpriv->is_611x || devpriv->is_6143) in ni_ai_insn_config()
2534 data[2] = board->ai_speed; in ni_ai_insn_config()
2540 return -EINVAL; in ni_ai_insn_config()
2547 struct comedi_cmd *cmd = &s->async->cmd; in ni_ao_munge()
2556 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]); in ni_ao_munge()
2572 chan_index %= cmd->chanlist_len; in ni_ao_munge()
2581 struct ni_private *devpriv = dev->private; in ni_m_series_ao_config_chanlist()
2589 for (i = 0; i < s->n_chan; ++i) { in ni_m_series_ao_config_chanlist()
2590 devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED; in ni_m_series_ao_config_chanlist()
2591 ni_writeb(dev, devpriv->ao_conf[i], in ni_m_series_ao_config_chanlist()
2601 krange = s->range_table->range + range; in ni_m_series_ao_config_chanlist()
2604 switch (krange->max - krange->min) { in ni_m_series_ao_config_chanlist()
2624 dev_err(dev->class_dev, in ni_m_series_ao_config_chanlist()
2628 switch (krange->max + krange->min) { in ni_m_series_ao_config_chanlist()
2636 dev_err(dev->class_dev, in ni_m_series_ao_config_chanlist()
2643 devpriv->ao_conf[chan] = conf; in ni_m_series_ao_config_chanlist()
2654 struct ni_private *devpriv = dev->private; in ni_old_ao_config_chanlist()
2668 invert = (s->maxdata + 1) >> 1; in ni_old_ao_config_chanlist()
2685 devpriv->ao_conf[chan] = conf; in ni_old_ao_config_chanlist()
2695 struct ni_private *devpriv = dev->private; in ni_ao_config_chanlist()
2697 if (devpriv->is_m_series) in ni_ao_config_chanlist()
2709 struct ni_private *devpriv = dev->private; in ni_ao_insn_write()
2710 unsigned int chan = CR_CHAN(insn->chanspec); in ni_ao_insn_write()
2711 unsigned int range = CR_RANGE(insn->chanspec); in ni_ao_insn_write()
2715 if (devpriv->is_6xxx) { in ni_ao_insn_write()
2719 } else if (devpriv->is_m_series) { in ni_ao_insn_write()
2725 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0); in ni_ao_insn_write()
2727 for (i = 0; i < insn->n; i++) { in ni_ao_insn_write()
2730 s->readback[chan] = val; in ni_ao_insn_write()
2732 if (devpriv->is_6xxx) { in ni_ao_insn_write()
2740 } else if (devpriv->is_m_series) { in ni_ao_insn_write()
2742 * M-series boards use offset binary values for in ni_ao_insn_write()
2748 * Non-M series boards need two's complement values in ni_ao_insn_write()
2758 return insn->n; in ni_ao_insn_write()
2774 struct ni_private *devpriv = dev->private; in ni_ao_arm()
2784 if (!devpriv->ao_needs_arming) { in ni_ao_arm()
2785 dev_dbg(dev->class_dev, "%s: device does not need arming!\n", in ni_ao_arm()
2787 return -EINVAL; in ni_ao_arm()
2790 devpriv->ao_needs_arming = 0; in ni_ao_arm()
2797 if (devpriv->is_6xxx) in ni_ao_arm()
2808 return -EPIPE; in ni_ao_arm()
2813 ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE, in ni_ao_arm()
2815 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG); in ni_ao_arm()
2824 dev_err(dev->class_dev, in ni_ao_arm()
2826 return -EIO; in ni_ao_arm()
2839 devpriv->ao_cmd1, in ni_ao_arm()
2849 const struct ni_board_struct *board = dev->board_ptr; in ni_ao_insn_config()
2850 struct ni_private *devpriv = dev->private; in ni_ao_insn_config()
2858 board->ao_fifo_depth); in ni_ao_insn_config()
2860 if (devpriv->mite) in ni_ao_insn_config()
2861 data[2] += devpriv->mite->fifo_size; in ni_ao_insn_config()
2867 return -EINVAL; in ni_ao_insn_config()
2875 data[1] = board->ao_speed * data[3]; in ni_ao_insn_config()
2882 return -EINVAL; in ni_ao_insn_config()
2889 struct ni_private *devpriv = dev->private; in ni_ao_inttrig()
2890 struct comedi_cmd *cmd = &s->async->cmd; in ni_ao_inttrig()
2894 * Require trig_num == cmd->start_arg when cmd->start_src == TRIG_INT. in ni_ao_inttrig()
2896 * cmd->start_src != TRIG_INT (i.e. when cmd->start_src == TRIG_EXT); in ni_ao_inttrig()
2897 * in that case, the internal trigger is being used as a pre-trigger in ni_ao_inttrig()
2900 if (!(trig_num == cmd->start_arg || in ni_ao_inttrig()
2901 (trig_num == 0 && cmd->start_src != TRIG_INT))) in ni_ao_inttrig()
2902 return -EINVAL; in ni_ao_inttrig()
2908 s->async->inttrig = NULL; in ni_ao_inttrig()
2910 if (devpriv->ao_needs_arming) { in ni_ao_inttrig()
2917 ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2, in ni_ao_inttrig()
2925 * Organized similar to NI-STC and MHDDK examples.
2926 * ni_ao_cmd is broken out into configuration sub-routines for clarity.
2932 const struct ni_board_struct *board = dev->board_ptr; in ni_ao_cmd_personalize()
2938 /* fast CPU interface--only eseries */ in ni_ao_cmd_personalize()
2954 (board->ao_fifo_depth ? in ni_ao_cmd_personalize()
2962 * sure if e-series all have duals... in ni_ao_cmd_personalize()
2969 if (devpriv->is_m_series) in ni_ao_cmd_personalize()
2980 struct ni_private *devpriv = dev->private; in ni_ao_cmd_set_trigger()
2986 if (cmd->stop_src == TRIG_NONE) { in ni_ao_cmd_set_trigger()
2987 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS; in ni_ao_cmd_set_trigger()
2988 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE; in ni_ao_cmd_set_trigger()
2990 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS; in ni_ao_cmd_set_trigger()
2991 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE; in ni_ao_cmd_set_trigger()
2993 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); in ni_ao_cmd_set_trigger()
2995 if (cmd->start_src == TRIG_INT) { in ni_ao_cmd_set_trigger()
3001 CR_CHAN(cmd->start_arg), in ni_ao_cmd_set_trigger()
3003 &devpriv->routing_tables, 1)); in ni_ao_cmd_set_trigger()
3005 /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */ in ni_ao_cmd_set_trigger()
3006 if (cmd->start_arg & CR_INVERT) in ni_ao_cmd_set_trigger()
3008 /* 0=edge detection disabled, 1=enabled */ in ni_ao_cmd_set_trigger()
3009 if (cmd->start_arg & CR_EDGE) in ni_ao_cmd_set_trigger()
3018 devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN; in ni_ao_cmd_set_trigger()
3019 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG); in ni_ao_cmd_set_trigger()
3027 struct ni_private *devpriv = dev->private; in ni_ao_cmd_set_counters()
3033 * set_trigger above. It is unclear whether we really need to re-write in ni_ao_cmd_set_counters()
3034 * this register with these values. The mhddk examples for e-series in ni_ao_cmd_set_counters()
3035 * show writing this in both places, but the examples for m-series show in ni_ao_cmd_set_counters()
3038 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); in ni_ao_cmd_set_counters()
3040 /* sync (upload number of buffer iterations -1) */ in ni_ao_cmd_set_counters()
3042 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC; in ni_ao_cmd_set_counters()
3043 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); in ni_ao_cmd_set_counters()
3052 /* sync (issue command to load number of buffer iterations -1) */ in ni_ao_cmd_set_counters()
3057 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC; in ni_ao_cmd_set_counters()
3058 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); in ni_ao_cmd_set_counters()
3069 unsigned int stop_arg = cmd->stop_arg > 0 ? in ni_ao_cmd_set_counters()
3070 (cmd->stop_arg & 0xffffff) : 0xffffff; in ni_ao_cmd_set_counters()
3072 if (devpriv->is_m_series) { in ni_ao_cmd_set_counters()
3074 * this is how the NI example code does it for m-series in ni_ao_cmd_set_counters()
3077 ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG); in ni_ao_cmd_set_counters()
3090 * sync (upload number of updates-1 in MISB) in ni_ao_cmd_set_counters()
3091 * --eseries only? in ni_ao_cmd_set_counters()
3093 ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG); in ni_ao_cmd_set_counters()
3103 struct ni_private *devpriv = dev->private; in ni_ao_cmd_set_update()
3108 * zero out these bit fields to be set below. Does an ao-reset do this in ni_ao_cmd_set_update()
3111 devpriv->ao_mode1 &= ~(NISTC_AO_MODE1_UI_SRC_MASK | in ni_ao_cmd_set_update()
3116 if (cmd->scan_begin_src == TRIG_TIMER) { in ni_ao_cmd_set_update()
3119 devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA; in ni_ao_cmd_set_update()
3131 * devpriv->ao_mode1 &= ~( in ni_ao_cmd_set_update()
3149 trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg, in ni_ao_cmd_set_update()
3156 /* following line: 2-1 per STC */ in ni_ao_cmd_set_update()
3161 /* FIXME: assert scan_begin_arg != 0, ret failure otherwise */ in ni_ao_cmd_set_update()
3162 devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA; in ni_ao_cmd_set_update()
3163 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC( in ni_ao_cmd_set_update()
3165 CR_CHAN(cmd->scan_begin_arg), in ni_ao_cmd_set_update()
3167 &devpriv->routing_tables)); in ni_ao_cmd_set_update()
3168 if (cmd->scan_begin_arg & CR_INVERT) in ni_ao_cmd_set_update()
3169 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY; in ni_ao_cmd_set_update()
3172 ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG); in ni_ao_cmd_set_update()
3173 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); in ni_ao_cmd_set_update()
3174 devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) | in ni_ao_cmd_set_update()
3176 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); in ni_ao_cmd_set_update()
3178 /* Configure DAQ-STC for Timed update mode */ in ni_ao_cmd_set_update()
3179 devpriv->ao_cmd1 |= NISTC_AO_CMD1_DAC1_UPDATE_MODE | in ni_ao_cmd_set_update()
3181 /* We are not using UPDATE2-->don't have to set DACx_Source_Select */ in ni_ao_cmd_set_update()
3182 ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG); in ni_ao_cmd_set_update()
3190 struct ni_private *devpriv = dev->private; in ni_ao_cmd_set_channels()
3191 const struct comedi_cmd *cmd = &s->async->cmd; in ni_ao_cmd_set_channels()
3196 if (devpriv->is_6xxx) { in ni_ao_cmd_set_channels()
3200 for (i = 0; i < cmd->chanlist_len; ++i) { in ni_ao_cmd_set_channels()
3201 int chan = CR_CHAN(cmd->chanlist[i]); in ni_ao_cmd_set_channels()
3209 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1); in ni_ao_cmd_set_channels()
3211 if (cmd->scan_end_arg > 1) { in ni_ao_cmd_set_channels()
3212 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN; in ni_ao_cmd_set_channels()
3213 bits = NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1) in ni_ao_cmd_set_channels()
3217 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN; in ni_ao_cmd_set_channels()
3219 if (devpriv->is_m_series | devpriv->is_6xxx) in ni_ao_cmd_set_channels()
3223 CR_CHAN(cmd->chanlist[0])); in ni_ao_cmd_set_channels()
3226 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); in ni_ao_cmd_set_channels()
3235 struct ni_private *devpriv = dev->private; in ni_ao_cmd_set_stop_conditions()
3239 devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR; in ni_ao_cmd_set_stop_conditions()
3240 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG); in ni_ao_cmd_set_stop_conditions()
3253 struct ni_private *devpriv = dev->private; in ni_ao_cmd_set_fifo_mode()
3257 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK; in ni_ao_cmd_set_fifo_mode()
3259 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F; in ni_ao_cmd_set_fifo_mode()
3261 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF; in ni_ao_cmd_set_fifo_mode()
3264 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA; in ni_ao_cmd_set_fifo_mode()
3265 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); in ni_ao_cmd_set_fifo_mode()
3278 if (s->async->cmd.stop_src == TRIG_COUNT) in ni_ao_cmd_set_interrupts()
3282 s->async->inttrig = ni_ao_inttrig; in ni_ao_cmd_set_interrupts()
3287 struct ni_private *devpriv = dev->private; in ni_ao_cmd()
3288 const struct comedi_cmd *cmd = &s->async->cmd; in ni_ao_cmd()
3290 if (dev->irq == 0) { in ni_ao_cmd()
3291 dev_err(dev->class_dev, "cannot run command without an irq"); in ni_ao_cmd()
3292 return -EIO; in ni_ao_cmd()
3305 ni_cmd_set_mite_transfer(devpriv->ao_mite_ring, s, cmd, 0x00ffffff); in ni_ao_cmd()
3319 devpriv->ao_needs_arming = 1; in ni_ao_cmd()
3328 const struct ni_board_struct *board = dev->board_ptr; in ni_ao_cmdtest()
3329 struct ni_private *devpriv = dev->private; in ni_ao_cmdtest()
3335 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT); in ni_ao_cmdtest()
3336 err |= comedi_check_trigger_src(&cmd->scan_begin_src, in ni_ao_cmdtest()
3338 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW); in ni_ao_cmdtest()
3339 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); in ni_ao_cmdtest()
3340 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); in ni_ao_cmdtest()
3347 err |= comedi_check_trigger_is_unique(cmd->start_src); in ni_ao_cmdtest()
3348 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src); in ni_ao_cmdtest()
3349 err |= comedi_check_trigger_is_unique(cmd->stop_src); in ni_ao_cmdtest()
3358 switch (cmd->start_src) { in ni_ao_cmdtest()
3360 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); in ni_ao_cmdtest()
3363 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->start_arg), in ni_ao_cmdtest()
3365 &devpriv->routing_tables, 1); in ni_ao_cmdtest()
3369 if (cmd->scan_begin_src == TRIG_TIMER) { in ni_ao_cmdtest()
3370 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg, in ni_ao_cmdtest()
3371 board->ao_speed); in ni_ao_cmdtest()
3372 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, in ni_ao_cmdtest()
3373 devpriv->clock_ns * in ni_ao_cmdtest()
3376 err |= ni_check_trigger_arg(CR_CHAN(cmd->scan_begin_arg), in ni_ao_cmdtest()
3378 &devpriv->routing_tables); in ni_ao_cmdtest()
3381 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0); in ni_ao_cmdtest()
3382 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, in ni_ao_cmdtest()
3383 cmd->chanlist_len); in ni_ao_cmdtest()
3384 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff); in ni_ao_cmdtest()
3390 if (cmd->scan_begin_src == TRIG_TIMER) { in ni_ao_cmdtest()
3391 tmp = cmd->scan_begin_arg; in ni_ao_cmdtest()
3392 cmd->scan_begin_arg = in ni_ao_cmdtest()
3394 cmd->scan_begin_arg, in ni_ao_cmdtest()
3395 cmd->flags)); in ni_ao_cmdtest()
3396 if (tmp != cmd->scan_begin_arg) in ni_ao_cmdtest()
3407 /* See 3.6.1.2 "Resetting", of DAQ-STC Technical Reference Manual */ in ni_ao_reset()
3410 * In the following, the "--sync" comments are meant to denote in ni_ao_reset()
3412 * DAQ-STC mostly in the order also described in the DAQ-STC. in ni_ao_reset()
3415 struct ni_private *devpriv = dev->private; in ni_ao_reset()
3419 /* --sync (reset AO) */ in ni_ao_reset()
3420 if (devpriv->is_m_series) in ni_ao_reset()
3421 /* following example in mhddk for m-series */ in ni_ao_reset()
3424 /*--sync (start config) */ in ni_ao_reset()
3427 /*--sync (Disarm) */ in ni_ao_reset()
3431 * --sync in ni_ao_reset()
3432 * (clear bunch of registers--mseries mhddk examples do not include in ni_ao_reset()
3435 devpriv->ao_cmd1 = 0; in ni_ao_reset()
3436 devpriv->ao_cmd2 = 0; in ni_ao_reset()
3437 devpriv->ao_mode1 = 0; in ni_ao_reset()
3438 devpriv->ao_mode2 = 0; in ni_ao_reset()
3439 if (devpriv->is_m_series) in ni_ao_reset()
3440 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE; in ni_ao_reset()
3442 devpriv->ao_mode3 = 0; in ni_ao_reset()
3450 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG); in ni_ao_reset()
3454 /*--sync (disable interrupts) */ in ni_ao_reset()
3457 /*--sync (ack) */ in ni_ao_reset()
3461 /*--not in DAQ-STC. which doc? */ in ni_ao_reset()
3462 if (devpriv->is_6xxx) { in ni_ao_reset()
3463 ni_ao_win_outw(dev, (1u << s->n_chan) - 1u, in ni_ao_reset()
3469 /*--end */ in ni_ao_reset()
3481 struct ni_private *devpriv = dev->private; in ni_dio_insn_config()
3488 devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK; in ni_dio_insn_config()
3489 devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits); in ni_dio_insn_config()
3490 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_dio_insn_config()
3492 return insn->n; in ni_dio_insn_config()
3500 struct ni_private *devpriv = dev->private; in ni_dio_insn_bits()
3504 devpriv->serial_interval_ns) in ni_dio_insn_bits()
3505 return -EBUSY; in ni_dio_insn_bits()
3508 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK; in ni_dio_insn_bits()
3509 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state); in ni_dio_insn_bits()
3510 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG); in ni_dio_insn_bits()
3515 return insn->n; in ni_dio_insn_bits()
3527 const struct ni_board_struct *board = dev->board_ptr; in ni_m_series_dio_insn_config()
3530 data[1] = board->dio_speed; in ni_m_series_dio_insn_config()
3539 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG); in ni_m_series_dio_insn_config()
3541 return insn->n; in ni_m_series_dio_insn_config()
3550 ni_writel(dev, s->state, NI_M_DIO_REG); in ni_m_series_dio_insn_bits()
3554 return insn->n; in ni_m_series_dio_insn_bits()
3563 for (i = 0; i < cmd->chanlist_len; ++i) { in ni_cdio_check_chanlist()
3564 unsigned int chan = CR_CHAN(cmd->chanlist[i]); in ni_cdio_check_chanlist()
3567 return -EINVAL; in ni_cdio_check_chanlist()
3576 struct ni_private *devpriv = dev->private; in ni_cdio_cmdtest()
3582 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT); in ni_cdio_cmdtest()
3583 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT); in ni_cdio_cmdtest()
3584 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW); in ni_cdio_cmdtest()
3585 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); in ni_cdio_cmdtest()
3586 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE); in ni_cdio_cmdtest()
3596 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); in ni_cdio_cmdtest()
3602 err |= ni_check_trigger_arg(CR_CHAN(cmd->scan_begin_arg), in ni_cdio_cmdtest()
3604 &devpriv->routing_tables); in ni_cdio_cmdtest()
3605 if (CR_RANGE(cmd->scan_begin_arg) != 0 || in ni_cdio_cmdtest()
3606 CR_AREF(cmd->scan_begin_arg) != 0) in ni_cdio_cmdtest()
3607 err |= -EINVAL; in ni_cdio_cmdtest()
3609 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0); in ni_cdio_cmdtest()
3610 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, in ni_cdio_cmdtest()
3611 cmd->chanlist_len); in ni_cdio_cmdtest()
3614 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, in ni_cdio_cmdtest()
3615 s->async->prealloc_bufsz / in ni_cdio_cmdtest()
3626 if (cmd->chanlist && cmd->chanlist_len > 0) in ni_cdio_cmdtest()
3639 struct comedi_cmd *cmd = &s->async->cmd; in ni_cdo_inttrig()
3643 struct ni_private *devpriv = dev->private; in ni_cdo_inttrig()
3646 if (trig_num != cmd->start_arg) in ni_cdo_inttrig()
3647 return -EINVAL; in ni_cdo_inttrig()
3649 s->async->inttrig = NULL; in ni_cdo_inttrig()
3652 comedi_buf_read_alloc(s, s->async->prealloc_bufsz); in ni_cdo_inttrig()
3654 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_cdo_inttrig()
3655 if (devpriv->cdo_mite_chan) { in ni_cdo_inttrig()
3656 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32); in ni_cdo_inttrig()
3657 mite_dma_arm(devpriv->cdo_mite_chan); in ni_cdo_inttrig()
3659 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n"); in ni_cdo_inttrig()
3660 retval = -EIO; in ni_cdo_inttrig()
3662 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_cdo_inttrig()
3678 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n"); in ni_cdo_inttrig()
3679 s->cancel(dev, s); in ni_cdo_inttrig()
3680 return -EIO; in ni_cdo_inttrig()
3691 struct ni_private *devpriv = dev->private; in ni_cdio_cmd()
3692 const struct comedi_cmd *cmd = &s->async->cmd; in ni_cdio_cmd()
3705 CR_CHAN(cmd->scan_begin_arg), in ni_cdio_cmd()
3707 &devpriv->routing_tables)); in ni_cdio_cmd()
3708 if (cmd->scan_begin_arg & CR_INVERT) in ni_cdio_cmd()
3711 if (s->io_bits) { in ni_cdio_cmd()
3712 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG); in ni_cdio_cmd()
3714 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG); in ni_cdio_cmd()
3716 dev_err(dev->class_dev, in ni_cdio_cmd()
3718 return -EIO; in ni_cdio_cmd()
3724 ni_cmd_set_mite_transfer(devpriv->cdo_mite_ring, s, cmd, in ni_cdio_cmd()
3725 s->async->prealloc_bufsz / in ni_cdio_cmd()
3728 s->async->inttrig = ni_cdo_inttrig; in ni_cdio_cmd()
3751 struct ni_private *devpriv = dev->private; in handle_cdio_interrupt()
3753 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV]; in handle_cdio_interrupt()
3756 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in handle_cdio_interrupt()
3757 if (devpriv->cdo_mite_chan) in handle_cdio_interrupt()
3758 mite_ack_linkc(devpriv->cdo_mite_chan, s, true); in handle_cdio_interrupt()
3759 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in handle_cdio_interrupt()
3766 s->async->events |= COMEDI_CB_OVERFLOW; in handle_cdio_interrupt()
3771 /* s->async->events |= COMEDI_CB_EOA; */ in handle_cdio_interrupt()
3782 struct ni_private *devpriv = dev->private; in ni_serial_hw_readwrite8()
3786 devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK; in ni_serial_hw_readwrite8()
3787 devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out); in ni_serial_hw_readwrite8()
3788 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG); in ni_serial_hw_readwrite8()
3792 err = -EBUSY; in ni_serial_hw_readwrite8()
3796 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START; in ni_serial_hw_readwrite8()
3797 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_serial_hw_readwrite8()
3798 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START; in ni_serial_hw_readwrite8()
3804 udelay((devpriv->serial_interval_ns + 999) / 1000); in ni_serial_hw_readwrite8()
3805 if (--count < 0) { in ni_serial_hw_readwrite8()
3806 dev_err(dev->class_dev, in ni_serial_hw_readwrite8()
3808 err = -ETIME; in ni_serial_hw_readwrite8()
3817 udelay((devpriv->serial_interval_ns + 999) / 1000); in ni_serial_hw_readwrite8()
3823 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_serial_hw_readwrite8()
3833 struct ni_private *devpriv = dev->private; in ni_serial_sw_readwrite8()
3837 udelay((devpriv->serial_interval_ns + 999) / 1000); in ni_serial_sw_readwrite8()
3841 * Output current bit; note that we cannot touch s->state in ni_serial_sw_readwrite8()
3842 * because it is a per-subdevice field, and serial is in ni_serial_sw_readwrite8()
3845 devpriv->dio_output &= ~NISTC_DIO_SDOUT; in ni_serial_sw_readwrite8()
3847 devpriv->dio_output |= NISTC_DIO_SDOUT; in ni_serial_sw_readwrite8()
3848 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG); in ni_serial_sw_readwrite8()
3851 * Assert SDCLK (active low, inverted), wait for half of in ni_serial_sw_readwrite8()
3854 devpriv->dio_control |= NISTC_DIO_SDCLK; in ni_serial_sw_readwrite8()
3855 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_serial_sw_readwrite8()
3857 udelay((devpriv->serial_interval_ns + 999) / 2000); in ni_serial_sw_readwrite8()
3859 devpriv->dio_control &= ~NISTC_DIO_SDCLK; in ni_serial_sw_readwrite8()
3860 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_serial_sw_readwrite8()
3862 udelay((devpriv->serial_interval_ns + 999) / 2000); in ni_serial_sw_readwrite8()
3880 struct ni_private *devpriv = dev->private; in ni_serial_insn_config()
3881 unsigned int clk_fout = devpriv->clock_and_fout; in ni_serial_insn_config()
3882 int err = insn->n; in ni_serial_insn_config()
3885 if (insn->n != 2) in ni_serial_insn_config()
3886 return -EINVAL; in ni_serial_insn_config()
3890 devpriv->serial_hw_mode = 1; in ni_serial_insn_config()
3891 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA; in ni_serial_insn_config()
3894 devpriv->serial_hw_mode = 0; in ni_serial_insn_config()
3895 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA | in ni_serial_insn_config()
3898 devpriv->serial_interval_ns = data[1]; in ni_serial_insn_config()
3904 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE; in ni_serial_insn_config()
3908 devpriv->serial_interval_ns = data[1]; in ni_serial_insn_config()
3910 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE; in ni_serial_insn_config()
3914 devpriv->serial_interval_ns = data[1]; in ni_serial_insn_config()
3916 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE; in ni_serial_insn_config()
3926 devpriv->serial_interval_ns = data[1]; in ni_serial_insn_config()
3928 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA | in ni_serial_insn_config()
3930 devpriv->serial_hw_mode = 0; in ni_serial_insn_config()
3932 devpriv->serial_interval_ns = data[1]; in ni_serial_insn_config()
3934 devpriv->clock_and_fout = clk_fout; in ni_serial_insn_config()
3936 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_serial_insn_config()
3937 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); in ni_serial_insn_config()
3942 if (devpriv->serial_interval_ns == 0) in ni_serial_insn_config()
3943 return -EINVAL; in ni_serial_insn_config()
3947 if (devpriv->serial_hw_mode) { in ni_serial_insn_config()
3950 } else if (devpriv->serial_interval_ns > 0) { in ni_serial_insn_config()
3954 dev_err(dev->class_dev, "serial disabled!\n"); in ni_serial_insn_config()
3955 return -EINVAL; in ni_serial_insn_config()
3960 return insn->n; in ni_serial_insn_config()
3964 return -EINVAL; in ni_serial_insn_config()
3972 for (i = 0; i < s->n_chan; i++) { in init_ao_67xx()
3996 [NITIO_G0_CNT_MODE] = { 0x1b0, 2 }, /* M-Series only */
3997 [NITIO_G1_CNT_MODE] = { 0x1b2, 2 }, /* M-Series only */
3998 [NITIO_G0_GATE2] = { 0x1b4, 2 }, /* M-Series only */
3999 [NITIO_G1_GATE2] = { 0x1b6, 2 }, /* M-Series only */
4004 [NITIO_G0_DMA_CFG] = { 0x1b8, 2 }, /* M-Series only */
4005 [NITIO_G1_DMA_CFG] = { 0x1ba, 2 }, /* M-Series only */
4006 [NITIO_G0_DMA_STATUS] = { 0x1b8, 2 }, /* M-Series only */
4007 [NITIO_G1_DMA_STATUS] = { 0x1ba, 2 }, /* M-Series only */
4008 [NITIO_G0_ABZ] = { 0x1c0, 2 }, /* M-Series only */
4009 [NITIO_G1_ABZ] = { 0x1c2, 2 }, /* M-Series only */
4026 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n", in ni_gpct_to_stc_register()
4031 return regmap->mio_reg; in ni_gpct_to_stc_register()
4037 struct comedi_device *dev = counter->counter_dev->dev; in ni_gpct_write_register()
4044 /* m-series only registers */ in ni_gpct_write_register()
4083 struct comedi_device *dev = counter->counter_dev->dev; in ni_gpct_read_register()
4090 /* m-series only registers */ in ni_gpct_read_register()
4113 struct ni_private *devpriv = dev->private; in ni_freq_out_insn_read()
4114 unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout); in ni_freq_out_insn_read()
4117 for (i = 0; i < insn->n; i++) in ni_freq_out_insn_read()
4120 return insn->n; in ni_freq_out_insn_read()
4128 struct ni_private *devpriv = dev->private; in ni_freq_out_insn_write()
4130 if (insn->n) { in ni_freq_out_insn_write()
4131 unsigned int val = data[insn->n - 1]; in ni_freq_out_insn_write()
4133 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA; in ni_freq_out_insn_write()
4134 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); in ni_freq_out_insn_write()
4135 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK; in ni_freq_out_insn_write()
4138 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val); in ni_freq_out_insn_write()
4140 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA; in ni_freq_out_insn_write()
4141 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); in ni_freq_out_insn_write()
4143 return insn->n; in ni_freq_out_insn_write()
4151 struct ni_private *devpriv = dev->private; in ni_freq_out_insn_config()
4157 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL; in ni_freq_out_insn_config()
4160 devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL; in ni_freq_out_insn_config()
4163 return -EINVAL; in ni_freq_out_insn_config()
4165 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); in ni_freq_out_insn_config()
4168 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) { in ni_freq_out_insn_config()
4177 return -EINVAL; in ni_freq_out_insn_config()
4179 return insn->n; in ni_freq_out_insn_config()
4195 struct ni_private *devpriv = dev->private; in ni_get_pwm_config()
4197 data[1] = devpriv->pwm_up_count * devpriv->clock_ns; in ni_get_pwm_config()
4198 data[2] = devpriv->pwm_down_count * devpriv->clock_ns; in ni_get_pwm_config()
4207 struct ni_private *devpriv = dev->private; in ni_m_series_pwm_config()
4215 devpriv->clock_ns); in ni_m_series_pwm_config()
4218 up_count = data[2] / devpriv->clock_ns; in ni_m_series_pwm_config()
4222 DIV_ROUND_UP(data[2], devpriv->clock_ns); in ni_m_series_pwm_config()
4225 return -EINVAL; in ni_m_series_pwm_config()
4230 devpriv->clock_ns); in ni_m_series_pwm_config()
4233 down_count = data[4] / devpriv->clock_ns; in ni_m_series_pwm_config()
4237 DIV_ROUND_UP(data[4], devpriv->clock_ns); in ni_m_series_pwm_config()
4240 return -EINVAL; in ni_m_series_pwm_config()
4242 if (up_count * devpriv->clock_ns != data[2] || in ni_m_series_pwm_config()
4243 down_count * devpriv->clock_ns != data[4]) { in ni_m_series_pwm_config()
4244 data[2] = up_count * devpriv->clock_ns; in ni_m_series_pwm_config()
4245 data[4] = down_count * devpriv->clock_ns; in ni_m_series_pwm_config()
4246 return -EAGAIN; in ni_m_series_pwm_config()
4251 devpriv->pwm_up_count = up_count; in ni_m_series_pwm_config()
4252 devpriv->pwm_down_count = down_count; in ni_m_series_pwm_config()
4257 return -EINVAL; in ni_m_series_pwm_config()
4267 struct ni_private *devpriv = dev->private; in ni_6143_pwm_config()
4275 devpriv->clock_ns); in ni_6143_pwm_config()
4278 up_count = data[2] / devpriv->clock_ns; in ni_6143_pwm_config()
4282 DIV_ROUND_UP(data[2], devpriv->clock_ns); in ni_6143_pwm_config()
4285 return -EINVAL; in ni_6143_pwm_config()
4290 devpriv->clock_ns); in ni_6143_pwm_config()
4293 down_count = data[4] / devpriv->clock_ns; in ni_6143_pwm_config()
4297 DIV_ROUND_UP(data[4], devpriv->clock_ns); in ni_6143_pwm_config()
4300 return -EINVAL; in ni_6143_pwm_config()
4302 if (up_count * devpriv->clock_ns != data[2] || in ni_6143_pwm_config()
4303 down_count * devpriv->clock_ns != data[4]) { in ni_6143_pwm_config()
4304 data[2] = up_count * devpriv->clock_ns; in ni_6143_pwm_config()
4305 data[4] = down_count * devpriv->clock_ns; in ni_6143_pwm_config()
4306 return -EAGAIN; in ni_6143_pwm_config()
4309 devpriv->pwm_up_count = up_count; in ni_6143_pwm_config()
4311 devpriv->pwm_down_count = down_count; in ni_6143_pwm_config()
4316 return -EINVAL; in ni_6143_pwm_config()
4329 * 1-12, whereas we use channel numbers 0-11. The NI in pack_mb88341()
4330 * docs use 1-12, also, so be careful here. in pack_mb88341()
4387 const struct ni_board_struct *board = dev->board_ptr; in ni_write_caldac()
4388 struct ni_private *devpriv = dev->private; in ni_write_caldac()
4394 if (devpriv->caldacs[addr] == val) in ni_write_caldac()
4396 devpriv->caldacs[addr] = val; in ni_write_caldac()
4399 type = board->caldac[i]; in ni_write_caldac()
4407 addr -= caldacs[type].n_chans; in ni_write_caldac()
4414 for (bit = 1 << (bits - 1); bit; bit >>= 1) { in ni_write_caldac()
4431 if (insn->n) { in ni_calib_insn_write()
4433 ni_write_caldac(dev, CR_CHAN(insn->chanspec), in ni_calib_insn_write()
4434 data[insn->n - 1]); in ni_calib_insn_write()
4437 return insn->n; in ni_calib_insn_write()
4445 struct ni_private *devpriv = dev->private; in ni_calib_insn_read()
4448 for (i = 0; i < insn->n; i++) in ni_calib_insn_read()
4449 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)]; in ni_calib_insn_read()
4451 return insn->n; in ni_calib_insn_read()
4456 const struct ni_board_struct *board = dev->board_ptr; in caldac_setup()
4457 struct ni_private *devpriv = dev->private; in caldac_setup()
4466 type = board->caldac[0]; in caldac_setup()
4471 type = board->caldac[i]; in caldac_setup()
4479 s->n_chan = n_chans; in caldac_setup()
4482 unsigned int *maxdata_list = devpriv->caldac_maxdata_list; in caldac_setup()
4485 dev_err(dev->class_dev, in caldac_setup()
4487 s->maxdata_list = maxdata_list; in caldac_setup()
4490 type = board->caldac[i]; in caldac_setup()
4493 (1 << caldacs[type].n_bits) - 1; in caldac_setup()
4498 for (chan = 0; chan < s->n_chan; chan++) in caldac_setup()
4499 ni_write_caldac(dev, i, s->maxdata_list[i] / 2); in caldac_setup()
4501 type = board->caldac[0]; in caldac_setup()
4502 s->maxdata = (1 << caldacs[type].n_bits) - 1; in caldac_setup()
4504 for (chan = 0; chan < s->n_chan; chan++) in caldac_setup()
4505 ni_write_caldac(dev, i, s->maxdata / 2); in caldac_setup()
4547 if (insn->n) { in ni_eeprom_insn_read()
4548 val = ni_read_eeprom(dev, CR_CHAN(insn->chanspec)); in ni_eeprom_insn_read()
4549 for (i = 0; i < insn->n; i++) in ni_eeprom_insn_read()
4552 return insn->n; in ni_eeprom_insn_read()
4560 struct ni_private *devpriv = dev->private; in ni_m_series_eeprom_insn_read()
4563 for (i = 0; i < insn->n; i++) in ni_m_series_eeprom_insn_read()
4564 data[i] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)]; in ni_m_series_eeprom_insn_read()
4566 return insn->n; in ni_m_series_eeprom_insn_read()
4572 /* pre-m-series boards have fixed signals on pfi pins */ in ni_old_get_pfi_routing()
4595 dev_err(dev->class_dev, "bug, unhandled case in switch.\n"); in ni_old_get_pfi_routing()
4604 /* pre-m-series boards have fixed signals on pfi pins */ in ni_old_set_pfi_routing()
4606 return -EINVAL; in ni_old_set_pfi_routing()
4613 struct ni_private *devpriv = dev->private; in ni_m_series_get_pfi_routing()
4617 devpriv->pfi_output_select_reg[array_offset]); in ni_m_series_get_pfi_routing()
4623 struct ni_private *devpriv = dev->private; in ni_m_series_set_pfi_routing()
4625 unsigned short val = devpriv->pfi_output_select_reg[index]; in ni_m_series_set_pfi_routing()
4628 return -EINVAL; in ni_m_series_set_pfi_routing()
4633 devpriv->pfi_output_select_reg[index] = val; in ni_m_series_set_pfi_routing()
4641 struct ni_private *devpriv = dev->private; in ni_get_pfi_routing()
4645 chan -= NI_PFI(0); in ni_get_pfi_routing()
4647 return (devpriv->is_m_series) in ni_get_pfi_routing()
4656 struct ni_private *devpriv = dev->private; in ni_set_pfi_routing()
4660 chan -= NI_PFI(0); in ni_set_pfi_routing()
4662 return (devpriv->is_m_series) in ni_set_pfi_routing()
4671 struct ni_private *devpriv = dev->private; in ni_config_pfi_filter()
4674 if (!devpriv->is_m_series) in ni_config_pfi_filter()
4675 return -ENOTSUPP; in ni_config_pfi_filter()
4679 chan -= NI_PFI(0); in ni_config_pfi_filter()
4694 chan -= NI_PFI(0); in ni_set_pfi_direction()
4702 struct ni_private *devpriv = dev->private; in ni_get_pfi_direction()
4706 chan -= NI_PFI(0); in ni_get_pfi_direction()
4708 return devpriv->io_bidirection_pin_reg & (1 << chan) ? in ni_get_pfi_direction()
4719 if (insn->n < 1) in ni_pfi_insn_config()
4720 return -EINVAL; in ni_pfi_insn_config()
4722 chan = CR_CHAN(insn->chanspec); in ni_pfi_insn_config()
4740 return -EINVAL; in ni_pfi_insn_config()
4750 struct ni_private *devpriv = dev->private; in ni_pfi_insn_bits()
4752 if (!devpriv->is_m_series) in ni_pfi_insn_bits()
4753 return -ENOTSUPP; in ni_pfi_insn_bits()
4756 ni_writew(dev, s->state, NI_M_PFI_DO_REG); in ni_pfi_insn_bits()
4760 return insn->n; in ni_pfi_insn_bits()
4775 return -EIO; in cs5529_wait_for_idle()
4778 dev_err(dev->class_dev, "timeout\n"); in cs5529_wait_for_idle()
4779 return -ETIME; in cs5529_wait_for_idle()
4801 dev_err(dev->class_dev, in cs5529_command()
4802 "possible problem - never saw adc go busy?\n"); in cs5529_command()
4814 dev_err(dev->class_dev, in cs5529_do_conversion()
4816 return -ETIME; in cs5529_do_conversion()
4820 dev_err(dev->class_dev, in cs5529_do_conversion()
4822 return -EIO; in cs5529_do_conversion()
4825 dev_err(dev->class_dev, in cs5529_do_conversion()
4852 if (insn->chanspec & CR_ALT_SOURCE) in cs5529_ai_insn_read()
4855 channel_select = CR_CHAN(insn->chanspec); in cs5529_ai_insn_read()
4858 for (n = 0; n < insn->n; n++) { in cs5529_ai_insn_read()
4864 return insn->n; in cs5529_ai_insn_read()
4875 dev_err(dev->class_dev, in cs5529_config_write()
4885 /* do self-calibration */ in init_cs5529()
4896 dev_err(dev->class_dev, in init_cs5529()
4919 * m-series wants the phased-locked loop to output 80MHz, which is in ni_mseries_get_pll_parameters()
4929 if (abs(new_period_ps - target_picosec) < in ni_mseries_get_pll_parameters()
4930 abs(best_period_picosec - target_picosec)) { in ni_mseries_get_pll_parameters()
4938 return -EIO; in ni_mseries_get_pll_parameters()
4952 struct ni_private *devpriv = dev->private; in ni_mseries_set_pll_master_clock()
4970 dev_err(dev->class_dev, in ni_mseries_set_pll_master_clock()
4971 …"%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\… in ni_mseries_set_pll_master_clock()
4973 return -EINVAL; in ni_mseries_set_pll_master_clock()
4975 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK; in ni_mseries_set_pll_master_clock()
4976 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, in ni_mseries_set_pll_master_clock()
4979 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL | in ni_mseries_set_pll_master_clock()
4981 devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK; in ni_mseries_set_pll_master_clock()
4984 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR; in ni_mseries_set_pll_master_clock()
4988 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10; in ni_mseries_set_pll_master_clock()
4993 devpriv->clock_and_fout2 |= in ni_mseries_set_pll_master_clock()
4999 return -EINVAL; in ni_mseries_set_pll_master_clock()
5005 &devpriv->clock_ns); in ni_mseries_set_pll_master_clock()
5007 dev_err(dev->class_dev, in ni_mseries_set_pll_master_clock()
5012 ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG); in ni_mseries_set_pll_master_clock()
5017 devpriv->clock_source = source; in ni_mseries_set_pll_master_clock()
5025 dev_err(dev->class_dev, in ni_mseries_set_pll_master_clock()
5028 return -ETIMEDOUT; in ni_mseries_set_pll_master_clock()
5036 struct ni_private *devpriv = dev->private; in ni_set_master_clock()
5039 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK; in ni_set_master_clock()
5040 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, in ni_set_master_clock()
5042 devpriv->clock_ns = TIMEBASE_1_NS; in ni_set_master_clock()
5043 if (devpriv->is_m_series) { in ni_set_master_clock()
5044 devpriv->clock_and_fout2 &= in ni_set_master_clock()
5047 ni_writew(dev, devpriv->clock_and_fout2, in ni_set_master_clock()
5051 devpriv->clock_source = source; in ni_set_master_clock()
5053 if (devpriv->is_m_series) { in ni_set_master_clock()
5058 devpriv->rtsi_trig_direction_reg |= in ni_set_master_clock()
5061 devpriv->rtsi_trig_direction_reg, in ni_set_master_clock()
5064 dev_err(dev->class_dev, in ni_set_master_clock()
5066 return -EINVAL; in ni_set_master_clock()
5068 devpriv->clock_ns = period_ns; in ni_set_master_clock()
5069 devpriv->clock_source = source; in ni_set_master_clock()
5071 return -EINVAL; in ni_set_master_clock()
5081 struct ni_private *devpriv = dev->private; in ni_valid_rtsi_output_source()
5083 if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) { in ni_valid_rtsi_output_source()
5088 dev_err(dev->class_dev, in ni_valid_rtsi_output_source()
5089 …"%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n", in ni_valid_rtsi_output_source()
5110 return (devpriv->is_m_series) ? 1 : 0; in ni_valid_rtsi_output_source()
5119 struct ni_private *devpriv = dev->private; in ni_set_rtsi_routing()
5123 chan -= TRIGGER_LINE(0); in ni_set_rtsi_routing()
5126 return -EINVAL; in ni_set_rtsi_routing()
5128 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan); in ni_set_rtsi_routing()
5129 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src); in ni_set_rtsi_routing()
5130 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg, in ni_set_rtsi_routing()
5132 } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) { in ni_set_rtsi_routing()
5133 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan); in ni_set_rtsi_routing()
5134 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src); in ni_set_rtsi_routing()
5135 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg, in ni_set_rtsi_routing()
5142 dev_err(dev->class_dev, "%s: unknown rtsi channel\n", __func__); in ni_set_rtsi_routing()
5143 return -EINVAL; in ni_set_rtsi_routing()
5151 struct ni_private *devpriv = dev->private; in ni_get_rtsi_routing()
5155 chan -= TRIGGER_LINE(0); in ni_get_rtsi_routing()
5159 devpriv->rtsi_trig_a_output_reg); in ni_get_rtsi_routing()
5160 } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) { in ni_get_rtsi_routing()
5162 devpriv->rtsi_trig_b_output_reg); in ni_get_rtsi_routing()
5167 dev_err(dev->class_dev, "%s: unknown rtsi channel\n", __func__); in ni_get_rtsi_routing()
5168 return -EINVAL; in ni_get_rtsi_routing()
5174 struct ni_private *devpriv = dev->private; in ni_set_rtsi_direction()
5175 unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series); in ni_set_rtsi_direction()
5179 chan -= TRIGGER_LINE(0); in ni_set_rtsi_direction()
5183 devpriv->rtsi_trig_direction_reg |= in ni_set_rtsi_direction()
5184 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series); in ni_set_rtsi_direction()
5186 devpriv->rtsi_trig_direction_reg |= in ni_set_rtsi_direction()
5191 devpriv->rtsi_trig_direction_reg &= in ni_set_rtsi_direction()
5192 ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series); in ni_set_rtsi_direction()
5194 devpriv->rtsi_trig_direction_reg &= in ni_set_rtsi_direction()
5198 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, in ni_set_rtsi_direction()
5204 struct ni_private *devpriv = dev->private; in ni_get_rtsi_direction()
5205 unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series); in ni_get_rtsi_direction()
5209 chan -= TRIGGER_LINE(0); in ni_get_rtsi_direction()
5212 return (devpriv->rtsi_trig_direction_reg & in ni_get_rtsi_direction()
5213 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series)) in ni_get_rtsi_direction()
5216 return (devpriv->rtsi_trig_direction_reg & in ni_get_rtsi_direction()
5220 return -EINVAL; in ni_get_rtsi_direction()
5228 struct ni_private *devpriv = dev->private; in ni_rtsi_insn_config()
5229 unsigned int chan = CR_CHAN(insn->chanspec); in ni_rtsi_insn_config()
5247 data[1] = devpriv->clock_source; in ni_rtsi_insn_config()
5248 data[2] = devpriv->clock_ns; in ni_rtsi_insn_config()
5261 return -EINVAL; in ni_rtsi_insn_config()
5273 return insn->n; in ni_rtsi_insn_bits()
5300 struct ni_private *devpriv = dev->private; in set_rgout0_reg()
5302 if (devpriv->is_m_series) { in set_rgout0_reg()
5303 devpriv->rtsi_trig_direction_reg &= in set_rgout0_reg()
5305 devpriv->rtsi_trig_direction_reg |= in set_rgout0_reg()
5308 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, in set_rgout0_reg()
5311 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIGB_SUB_SEL1; in set_rgout0_reg()
5312 devpriv->rtsi_trig_b_output_reg |= in set_rgout0_reg()
5315 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg, in set_rgout0_reg()
5322 struct ni_private *devpriv = dev->private; in get_rgout0_reg()
5325 if (devpriv->is_m_series) in get_rgout0_reg()
5326 reg = (devpriv->rtsi_trig_direction_reg & in get_rgout0_reg()
5330 reg = (devpriv->rtsi_trig_b_output_reg & in get_rgout0_reg()
5338 struct ni_private *devpriv = dev->private; in get_rgout0_src()
5341 return ni_find_route_source(reg, NI_RGOUT0, &devpriv->routing_tables); in get_rgout0_src()
5347 * @src: device-global signal name
5350 * Return: -EINVAL if the source is not valid to route to RGOUT0;
5351 * -EBUSY if the RGOUT0 is already used;
5356 struct ni_private *devpriv = dev->private; in incr_rgout0_src_use()
5358 &devpriv->routing_tables); in incr_rgout0_src_use()
5361 return -EINVAL; in incr_rgout0_src_use()
5363 if (devpriv->rgout0_usage > 0 && get_rgout0_reg(dev) != reg) in incr_rgout0_src_use()
5364 return -EBUSY; in incr_rgout0_src_use()
5366 ++devpriv->rgout0_usage; in incr_rgout0_src_use()
5375 * counter for the current src->RGOUT0 mapping.
5377 * Return: -EINVAL if the source is not already routed to RGOUT0 (or usage is
5382 struct ni_private *devpriv = dev->private; in decr_rgout0_src_use()
5384 &devpriv->routing_tables); in decr_rgout0_src_use()
5386 if (devpriv->rgout0_usage > 0 && get_rgout0_reg(dev) == reg) { in decr_rgout0_src_use()
5387 --devpriv->rgout0_usage; in decr_rgout0_src_use()
5388 if (!devpriv->rgout0_usage) in decr_rgout0_src_use()
5392 return -EINVAL; in decr_rgout0_src_use()
5403 struct ni_private *devpriv = dev->private; in set_ith_rtsi_brd_reg()
5404 int reg_i_sz = 3; /* value for e-series */ in set_ith_rtsi_brd_reg()
5408 if (devpriv->is_m_series) in set_ith_rtsi_brd_reg()
5414 devpriv->rtsi_shared_mux_reg &= ~(reg_i_mask << reg_i_shift); in set_ith_rtsi_brd_reg()
5416 devpriv->rtsi_shared_mux_reg |= (reg & reg_i_mask) << reg_i_shift; in set_ith_rtsi_brd_reg()
5418 ni_stc_writew(dev, devpriv->rtsi_shared_mux_reg, NISTC_RTSI_BOARD_REG); in set_ith_rtsi_brd_reg()
5423 struct ni_private *devpriv = dev->private; in get_ith_rtsi_brd_reg()
5424 int reg_i_sz = 3; /* value for e-series */ in get_ith_rtsi_brd_reg()
5428 if (devpriv->is_m_series) in get_ith_rtsi_brd_reg()
5433 return (devpriv->rtsi_shared_mux_reg >> reg_i_shift) & reg_i_mask; in get_ith_rtsi_brd_reg()
5438 struct ni_private *devpriv = dev->private; in get_rtsi_brd_src()
5443 brd_index = brd - NI_RTSI_BRD(0); in get_rtsi_brd_src()
5448 * brd : device-global name in get_rtsi_brd_src()
5454 return ni_find_route_source(reg, brd, &devpriv->routing_tables); in get_rtsi_brd_src()
5461 * Return: -EINVAL if the source is not valid to route to NI_RTSI_BRD(i);
5462 * -EBUSY if all NI_RTSI_BRD muxes are already used;
5467 struct ni_private *devpriv = dev->private; in incr_rtsi_brd_src_use()
5468 int first_available = -1; in incr_rtsi_brd_src_use()
5469 int err = -EINVAL; in incr_rtsi_brd_src_use()
5476 &devpriv->routing_tables); in incr_rtsi_brd_src_use()
5481 if (!devpriv->rtsi_shared_mux_usage[i]) { in incr_rtsi_brd_src_use()
5488 * final error to -EBUSY in case there are no muxes in incr_rtsi_brd_src_use()
5491 err = -EBUSY; in incr_rtsi_brd_src_use()
5510 ++devpriv->rtsi_shared_mux_usage[i]; in incr_rtsi_brd_src_use()
5519 * Return: -EINVAL if the source is not already routed to rtsi_brd(i) (or usage
5525 struct ni_private *devpriv = dev->private; in decr_rtsi_brd_src_use()
5527 &devpriv->routing_tables); in decr_rtsi_brd_src_use()
5528 const int i = rtsi_brd - NI_RTSI_BRD(0); in decr_rtsi_brd_src_use()
5530 if (devpriv->rtsi_shared_mux_usage[i] > 0 && in decr_rtsi_brd_src_use()
5532 --devpriv->rtsi_shared_mux_usage[i]; in decr_rtsi_brd_src_use()
5533 if (!devpriv->rtsi_shared_mux_usage[i]) in decr_rtsi_brd_src_use()
5538 return -EINVAL; in decr_rtsi_brd_src_use()
5543 struct ni_private *devpriv = dev->private; in ni_rtsi_init()
5550 * to have no effect, at least on pxi-6281, which always uses in ni_rtsi_init()
5553 devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ; in ni_rtsi_init()
5556 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n"); in ni_rtsi_init()
5567 * for e-series: in ni_rtsi_init()
5570 * for m-series: in ni_rtsi_init()
5573 devpriv->rtsi_shared_mux_reg = 0; in ni_rtsi_init()
5576 memset(devpriv->rtsi_shared_mux_usage, 0, in ni_rtsi_init()
5577 sizeof(devpriv->rtsi_shared_mux_usage)); in ni_rtsi_init()
5580 devpriv->rgout0_usage = 0; in ni_rtsi_init()
5588 struct ni_private *devpriv = dev->private; in ni_get_gout_routing()
5589 unsigned int reg = devpriv->an_trig_etc_reg; in ni_get_gout_routing()
5602 return -EINVAL; in ni_get_gout_routing()
5609 struct ni_private *devpriv = dev->private; in ni_disable_gout_routing()
5613 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_0_ENA; in ni_disable_gout_routing()
5616 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_1_ENA; in ni_disable_gout_routing()
5619 return -EINVAL; in ni_disable_gout_routing()
5622 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG); in ni_disable_gout_routing()
5630 struct ni_private *devpriv = dev->private; in ni_set_gout_routing()
5635 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_0_SEL(-1); in ni_set_gout_routing()
5637 devpriv->an_trig_etc_reg |= NISTC_ATRIG_ETC_GPFO_0_ENA in ni_set_gout_routing()
5642 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_1_SEL; in ni_set_gout_routing()
5645 devpriv->an_trig_etc_reg |= NISTC_ATRIG_ETC_GPFO_1_ENA | src; in ni_set_gout_routing()
5648 return -EINVAL; in ni_set_gout_routing()
5651 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG); in ni_set_gout_routing()
5658 * as an output, this function returns -EINVAL as error.
5661 * -EINVAL if terminal is not configured for output.
5665 struct ni_private *devpriv = dev->private; in get_output_select_source()
5666 int reg = -1; in get_output_select_source()
5680 const int i = reg - NI_RTSI_OUTPUT_RTSI_BRD(0); in get_output_select_source()
5686 } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) { in get_output_select_source()
5691 dest -= NI_CtrOut(0); in get_output_select_source()
5694 return -EINVAL; in get_output_select_source()
5697 reg = ni_tio_get_routing(devpriv->counter_dev, dest); in get_output_select_source()
5699 dev_dbg(dev->class_dev, "%s: unhandled destination (%d) queried\n", in get_output_select_source()
5705 &devpriv->routing_tables); in get_output_select_source()
5706 return -EINVAL; in get_output_select_source()
5712 * Return: -1 if not connectible;
5719 struct ni_private *devpriv = dev->private; in test_route()
5721 &devpriv->routing_tables); in test_route()
5724 return -1; in test_route()
5734 struct ni_private *devpriv = dev->private; in connect_route()
5736 &devpriv->routing_tables); in connect_route()
5741 return -EINVAL; in connect_route()
5745 return -EALREADY; in connect_route()
5748 return -EBUSY; in connect_route()
5762 /* Attempt to allocate and route (src->brd) */ in connect_route()
5768 /* Now lookup the register value for (brd->dest) */ in connect_route()
5770 brd, dest, &devpriv->routing_tables); in connect_route()
5775 } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) { in connect_route()
5780 dest -= NI_CtrOut(0); in connect_route()
5783 return -EINVAL; in connect_route()
5785 return -EINVAL; in connect_route()
5789 * invert/edge info passed by the user in connect_route()
5791 ni_tio_set_routing(devpriv->counter_dev, dest, in connect_route()
5792 reg | (src & ~CR_CHAN(-1))); in connect_route()
5794 return -EINVAL; in connect_route()
5802 struct ni_private *devpriv = dev->private; in disconnect_route()
5804 &devpriv->routing_tables); in disconnect_route()
5808 return -EINVAL; in disconnect_route()
5811 return -EINVAL; in disconnect_route()
5828 &devpriv->routing_tables); in disconnect_route()
5838 reg = default_rtsi_routing[dest - TRIGGER_LINE(0)]; in disconnect_route()
5841 } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) { in disconnect_route()
5846 dest -= NI_CtrOut(0); in disconnect_route()
5849 return -EINVAL; in disconnect_route()
5852 ni_tio_unset_routing(devpriv->counter_dev, dest); in disconnect_route()
5854 return -EINVAL; in disconnect_route()
5876 return -EINVAL; in ni_global_insn_config()
5884 struct ni_gpct *counter = s->private; in ni_gpct_cmd()
5887 retval = ni_request_gpct_mite_channel(dev, counter->counter_index, in ni_gpct_cmd()
5890 dev_err(dev->class_dev, in ni_gpct_cmd()
5895 ni_e_series_enable_second_irq(dev, counter->counter_index, 1); in ni_gpct_cmd()
5902 struct ni_gpct *counter = s->private; in ni_gpct_cancel()
5906 ni_e_series_enable_second_irq(dev, counter->counter_index, 0); in ni_gpct_cancel()
5907 ni_release_gpct_mite_channel(dev, counter->counter_index); in ni_gpct_cancel()
5915 struct comedi_subdevice *s_ai = dev->read_subdev; in ni_E_interrupt()
5916 struct comedi_subdevice *s_ao = dev->write_subdev; in ni_E_interrupt()
5921 struct ni_private *devpriv = dev->private; in ni_E_interrupt()
5924 if (!dev->attached) in ni_E_interrupt()
5926 smp_mb(); /* make sure dev->attached is checked */ in ni_E_interrupt()
5929 spin_lock_irqsave(&dev->spinlock, flags); in ni_E_interrupt()
5933 if (devpriv->mite) { in ni_E_interrupt()
5936 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too); in ni_E_interrupt()
5937 if (s_ai && devpriv->ai_mite_chan) in ni_E_interrupt()
5938 mite_ack_linkc(devpriv->ai_mite_chan, s_ai, false); in ni_E_interrupt()
5939 if (s_ao && devpriv->ao_mite_chan) in ni_E_interrupt()
5940 mite_ack_linkc(devpriv->ao_mite_chan, s_ao, false); in ni_E_interrupt()
5941 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too); in ni_E_interrupt()
5961 if (devpriv->is_m_series) in ni_E_interrupt()
5965 spin_unlock_irqrestore(&dev->spinlock, flags); in ni_E_interrupt()
5975 return -ENOMEM; in ni_alloc_private()
5977 spin_lock_init(&devpriv->window_lock); in ni_alloc_private()
5978 spin_lock_init(&devpriv->soft_reg_copy_lock); in ni_alloc_private()
5979 spin_lock_init(&devpriv->mite_channel_lock); in ni_alloc_private()
5988 struct ni_private *devpriv = dev->private; in _ni_get_valid_routes()
5990 return ni_get_valid_routes(&devpriv->routing_tables, n_pairs, in _ni_get_valid_routes()
5997 const struct ni_board_struct *board = dev->board_ptr; in ni_E_init()
5998 struct ni_private *devpriv = dev->private; in ni_E_init()
6002 const char *dev_family = devpriv->is_m_series ? "ni_mseries" in ni_E_init()
6004 if (!IS_PCIMIO != !dev->mmio) { in ni_E_init()
6005 dev_err(dev->class_dev, in ni_E_init()
6007 KBUILD_MODNAME, board->name); in ni_E_init()
6008 return -ENXIO; in ni_E_init()
6011 /* prepare the device for globally-named routes. */ in ni_E_init()
6012 if (ni_assign_device_routes(dev_family, board->name, in ni_E_init()
6013 board->alt_route_name, in ni_E_init()
6014 &devpriv->routing_tables) < 0) { in ni_E_init()
6015 dev_warn(dev->class_dev, "%s: %s device has no signal routing table.\n", in ni_E_init()
6016 __func__, board->name); in ni_E_init()
6017 …dev_warn(dev->class_dev, "%s: High level NI signal names will not be available for this %s board.\… in ni_E_init()
6018 __func__, board->name); in ni_E_init()
6024 dev->insn_device_config = ni_global_insn_config; in ni_E_init()
6025 dev->get_valid_routes = _ni_get_valid_routes; in ni_E_init()
6028 if (board->n_aochan > MAX_N_AO_CHAN) { in ni_E_init()
6029 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n"); in ni_E_init()
6030 return -EINVAL; in ni_E_init()
6034 devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 | in ni_E_init()
6038 if (!devpriv->is_6xxx) { in ni_E_init()
6039 /* BEAM is this needed for PCI-6143 ?? */ in ni_E_init()
6040 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 | in ni_E_init()
6043 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); in ni_E_init()
6050 s = &dev->subdevices[NI_AI_SUBDEV]; in ni_E_init()
6051 if (board->n_adchan) { in ni_E_init()
6052 s->type = COMEDI_SUBD_AI; in ni_E_init()
6053 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER; in ni_E_init()
6054 if (!devpriv->is_611x) in ni_E_init()
6055 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER; in ni_E_init()
6056 if (board->ai_maxdata > 0xffff) in ni_E_init()
6057 s->subdev_flags |= SDF_LSAMPL; in ni_E_init()
6058 if (devpriv->is_m_series) in ni_E_init()
6059 s->subdev_flags |= SDF_SOFT_CALIBRATED; in ni_E_init()
6060 s->n_chan = board->n_adchan; in ni_E_init()
6061 s->maxdata = board->ai_maxdata; in ni_E_init()
6062 s->range_table = ni_range_lkup[board->gainlkup]; in ni_E_init()
6063 s->insn_read = ni_ai_insn_read; in ni_E_init()
6064 s->insn_config = ni_ai_insn_config; in ni_E_init()
6065 if (dev->irq) { in ni_E_init()
6066 dev->read_subdev = s; in ni_E_init()
6067 s->subdev_flags |= SDF_CMD_READ; in ni_E_init()
6068 s->len_chanlist = 512; in ni_E_init()
6069 s->do_cmdtest = ni_ai_cmdtest; in ni_E_init()
6070 s->do_cmd = ni_ai_cmd; in ni_E_init()
6071 s->cancel = ni_ai_reset; in ni_E_init()
6072 s->poll = ni_ai_poll; in ni_E_init()
6073 s->munge = ni_ai_munge; in ni_E_init()
6075 if (devpriv->mite) in ni_E_init()
6076 s->async_dma_dir = DMA_FROM_DEVICE; in ni_E_init()
6082 s->type = COMEDI_SUBD_UNUSED; in ni_E_init()
6086 s = &dev->subdevices[NI_AO_SUBDEV]; in ni_E_init()
6087 if (board->n_aochan) { in ni_E_init()
6088 s->type = COMEDI_SUBD_AO; in ni_E_init()
6089 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND; in ni_E_init()
6090 if (devpriv->is_m_series) in ni_E_init()
6091 s->subdev_flags |= SDF_SOFT_CALIBRATED; in ni_E_init()
6092 s->n_chan = board->n_aochan; in ni_E_init()
6093 s->maxdata = board->ao_maxdata; in ni_E_init()
6094 s->range_table = board->ao_range_table; in ni_E_init()
6095 s->insn_config = ni_ao_insn_config; in ni_E_init()
6096 s->insn_write = ni_ao_insn_write; in ni_E_init()
6106 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) { in ni_E_init()
6107 dev->write_subdev = s; in ni_E_init()
6108 s->subdev_flags |= SDF_CMD_WRITE; in ni_E_init()
6109 s->len_chanlist = s->n_chan; in ni_E_init()
6110 s->do_cmdtest = ni_ao_cmdtest; in ni_E_init()
6111 s->do_cmd = ni_ao_cmd; in ni_E_init()
6112 s->cancel = ni_ao_reset; in ni_E_init()
6113 if (!devpriv->is_m_series) in ni_E_init()
6114 s->munge = ni_ao_munge; in ni_E_init()
6116 if (devpriv->mite) in ni_E_init()
6117 s->async_dma_dir = DMA_TO_DEVICE; in ni_E_init()
6120 if (devpriv->is_67xx) in ni_E_init()
6126 s->type = COMEDI_SUBD_UNUSED; in ni_E_init()
6130 s = &dev->subdevices[NI_DIO_SUBDEV]; in ni_E_init()
6131 s->type = COMEDI_SUBD_DIO; in ni_E_init()
6132 s->subdev_flags = SDF_WRITABLE | SDF_READABLE; in ni_E_init()
6133 s->n_chan = board->has_32dio_chan ? 32 : 8; in ni_E_init()
6134 s->maxdata = 1; in ni_E_init()
6135 s->range_table = &range_digital; in ni_E_init()
6136 if (devpriv->is_m_series) { in ni_E_init()
6138 s->subdev_flags |= SDF_LSAMPL; in ni_E_init()
6139 s->insn_bits = ni_m_series_dio_insn_bits; in ni_E_init()
6140 s->insn_config = ni_m_series_dio_insn_config; in ni_E_init()
6141 if (dev->irq) { in ni_E_init()
6142 s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */; in ni_E_init()
6143 s->len_chanlist = s->n_chan; in ni_E_init()
6144 s->do_cmdtest = ni_cdio_cmdtest; in ni_E_init()
6145 s->do_cmd = ni_cdio_cmd; in ni_E_init()
6146 s->cancel = ni_cdio_cancel; in ni_E_init()
6148 /* M-series boards use DMA */ in ni_E_init()
6149 s->async_dma_dir = DMA_BIDIRECTIONAL; in ni_E_init()
6156 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG); in ni_E_init()
6159 s->insn_bits = ni_dio_insn_bits; in ni_E_init()
6160 s->insn_config = ni_dio_insn_config; in ni_E_init()
6163 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits); in ni_E_init()
6164 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_E_init()
6168 s = &dev->subdevices[NI_8255_DIO_SUBDEV]; in ni_E_init()
6169 if (board->has_8255) { in ni_E_init()
6175 s->type = COMEDI_SUBD_UNUSED; in ni_E_init()
6179 s = &dev->subdevices[NI_UNUSED_SUBDEV]; in ni_E_init()
6180 s->type = COMEDI_SUBD_UNUSED; in ni_E_init()
6183 s = &dev->subdevices[NI_CALIBRATION_SUBDEV]; in ni_E_init()
6184 s->type = COMEDI_SUBD_CALIB; in ni_E_init()
6185 s->subdev_flags = SDF_INTERNAL; in ni_E_init()
6186 s->n_chan = 1; in ni_E_init()
6187 s->maxdata = 0; in ni_E_init()
6188 if (devpriv->is_m_series) { in ni_E_init()
6190 s->insn_config = ni_m_series_pwm_config; in ni_E_init()
6193 } else if (devpriv->is_6143) { in ni_E_init()
6195 s->insn_config = ni_6143_pwm_config; in ni_E_init()
6197 s->subdev_flags |= SDF_WRITABLE; in ni_E_init()
6198 s->insn_read = ni_calib_insn_read; in ni_E_init()
6199 s->insn_write = ni_calib_insn_write; in ni_E_init()
6206 s = &dev->subdevices[NI_EEPROM_SUBDEV]; in ni_E_init()
6207 s->type = COMEDI_SUBD_MEMORY; in ni_E_init()
6208 s->subdev_flags = SDF_READABLE | SDF_INTERNAL; in ni_E_init()
6209 s->maxdata = 0xff; in ni_E_init()
6210 if (devpriv->is_m_series) { in ni_E_init()
6211 s->n_chan = M_SERIES_EEPROM_SIZE; in ni_E_init()
6212 s->insn_read = ni_m_series_eeprom_insn_read; in ni_E_init()
6214 s->n_chan = 512; in ni_E_init()
6215 s->insn_read = ni_eeprom_insn_read; in ni_E_init()
6219 s = &dev->subdevices[NI_PFI_DIO_SUBDEV]; in ni_E_init()
6220 s->type = COMEDI_SUBD_DIO; in ni_E_init()
6221 s->maxdata = 1; in ni_E_init()
6222 if (devpriv->is_m_series) { in ni_E_init()
6223 s->n_chan = 16; in ni_E_init()
6224 s->insn_bits = ni_pfi_insn_bits; in ni_E_init()
6225 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; in ni_E_init()
6227 ni_writew(dev, s->state, NI_M_PFI_DO_REG); in ni_E_init()
6229 ni_writew(dev, devpriv->pfi_output_select_reg[i], in ni_E_init()
6233 s->n_chan = 10; in ni_E_init()
6234 s->subdev_flags = SDF_INTERNAL; in ni_E_init()
6236 s->insn_config = ni_pfi_insn_config; in ni_E_init()
6241 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV]; in ni_E_init()
6242 if (devpriv->is_67xx) { in ni_E_init()
6243 s->type = COMEDI_SUBD_AI; in ni_E_init()
6244 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL; in ni_E_init()
6246 s->n_chan = board->n_aochan; in ni_E_init()
6247 s->maxdata = BIT(16) - 1; in ni_E_init()
6248 s->range_table = &range_unknown; /* XXX */ in ni_E_init()
6249 s->insn_read = cs5529_ai_insn_read; in ni_E_init()
6250 s->insn_config = NULL; in ni_E_init()
6253 s->type = COMEDI_SUBD_UNUSED; in ni_E_init()
6257 s = &dev->subdevices[NI_SERIAL_SUBDEV]; in ni_E_init()
6258 s->type = COMEDI_SUBD_SERIAL; in ni_E_init()
6259 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; in ni_E_init()
6260 s->n_chan = 1; in ni_E_init()
6261 s->maxdata = 0xff; in ni_E_init()
6262 s->insn_config = ni_serial_insn_config; in ni_E_init()
6263 devpriv->serial_interval_ns = 0; in ni_E_init()
6264 devpriv->serial_hw_mode = 0; in ni_E_init()
6267 s = &dev->subdevices[NI_RTSI_SUBDEV]; in ni_E_init()
6268 s->type = COMEDI_SUBD_DIO; in ni_E_init()
6269 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; in ni_E_init()
6270 s->n_chan = 8; in ni_E_init()
6271 s->maxdata = 1; in ni_E_init()
6272 s->insn_bits = ni_rtsi_insn_bits; in ni_E_init()
6273 s->insn_config = ni_rtsi_insn_config; in ni_E_init()
6277 devpriv->counter_dev = ni_gpct_device_construct(dev, in ni_E_init()
6280 (devpriv->is_m_series) in ni_E_init()
6285 &devpriv->routing_tables); in ni_E_init()
6286 if (!devpriv->counter_dev) in ni_E_init()
6287 return -ENOMEM; in ni_E_init()
6291 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i]; in ni_E_init()
6296 s = &dev->subdevices[NI_GPCT_SUBDEV(i)]; in ni_E_init()
6297 s->type = COMEDI_SUBD_COUNTER; in ni_E_init()
6298 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL; in ni_E_init()
6299 s->n_chan = 3; in ni_E_init()
6300 s->maxdata = (devpriv->is_m_series) ? 0xffffffff in ni_E_init()
6302 s->insn_read = ni_tio_insn_read; in ni_E_init()
6303 s->insn_write = ni_tio_insn_write; in ni_E_init()
6304 s->insn_config = ni_tio_insn_config; in ni_E_init()
6306 if (dev->irq && devpriv->mite) { in ni_E_init()
6307 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */; in ni_E_init()
6308 s->len_chanlist = 1; in ni_E_init()
6309 s->do_cmdtest = ni_tio_cmdtest; in ni_E_init()
6310 s->do_cmd = ni_gpct_cmd; in ni_E_init()
6311 s->cancel = ni_gpct_cancel; in ni_E_init()
6313 s->async_dma_dir = DMA_BIDIRECTIONAL; in ni_E_init()
6316 s->private = gpct; in ni_E_init()
6324 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV]; in ni_E_init()
6325 s->type = COMEDI_SUBD_COUNTER; in ni_E_init()
6326 s->subdev_flags = SDF_READABLE | SDF_WRITABLE; in ni_E_init()
6327 s->n_chan = 1; in ni_E_init()
6328 s->maxdata = 0xf; in ni_E_init()
6329 s->insn_read = ni_freq_out_insn_read; in ni_E_init()
6330 s->insn_write = ni_freq_out_insn_write; in ni_E_init()
6331 s->insn_config = ni_freq_out_insn_config; in ni_E_init()
6333 if (dev->irq) { in ni_E_init()
6345 ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG); in ni_E_init()
6346 ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG); in ni_E_init()
6348 if (devpriv->is_6xxx) { in ni_E_init()
6350 } else if (devpriv->is_m_series) { in ni_E_init()
6353 for (channel = 0; channel < board->n_aochan; ++channel) { in ni_E_init()
6367 struct ni_private *devpriv = dev->private; in mio_common_detach()
6370 ni_gpct_device_destroy(devpriv->counter_dev); in mio_common_detach()