85 /* Divider limits, from UG572 Table 3-4 for Ultrascale+ */
111 /* Extract divider instance from clock hardware instance */
147  * struct clk_wzrd_divider - clock divider specific to clk_wzrd
150  * @base:	base address of register containing the divider
151  * @offset:	offset address of register containing the divider
152  * @shift:	shift to the divider bit field
153  * @width:	width of the divider bit field
154  * @flags:	clk_wzrd divider flags
155  * @table:	array of value/divider pairs, last entry should have div = 0
157  * @d:	value of the common divider
158  * @o:	value of the leaf divider
172 	spinlock_t *lock;  /* divider lock */
194 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_recalc_rate_ver()  local
195 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_recalc_rate_ver()
219 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_recalc_rate()  local
220 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_recalc_rate()
223 	val = readl(div_addr) >> divider->shift;  in clk_wzrd_recalc_rate()
224 	val &= div_mask(divider->width);  in clk_wzrd_recalc_rate()
226 	return divider_recalc_rate(hw, parent_rate, val, divider->table,  in clk_wzrd_recalc_rate()
227 			divider->flags, divider->width);  in clk_wzrd_recalc_rate()
233 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_ver_dynamic_reconfig()  local
234 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_ver_dynamic_reconfig()
239 	spin_lock_irqsave(divider->lock, flags);  in clk_wzrd_ver_dynamic_reconfig()
259 	err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,  in clk_wzrd_ver_dynamic_reconfig()
267 	       divider->base + WZRD_DR_INIT_VERSAL_OFFSET);  in clk_wzrd_ver_dynamic_reconfig()
270 	err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,  in clk_wzrd_ver_dynamic_reconfig()
274 	spin_unlock_irqrestore(divider->lock, flags);  in clk_wzrd_ver_dynamic_reconfig()
281 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_reconfig()  local
282 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_dynamic_reconfig()
287 	spin_lock_irqsave(divider->lock, flags);  in clk_wzrd_dynamic_reconfig()
299 	err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,  in clk_wzrd_dynamic_reconfig()
307 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_reconfig()
309 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_reconfig()
312 	err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,  in clk_wzrd_dynamic_reconfig()
316 	spin_unlock_irqrestore(divider->lock, flags);  in clk_wzrd_dynamic_reconfig()
337 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_get_divisors_ver()  local
360 						divider->m = m;  in clk_wzrd_get_divisors_ver()
361 						divider->d = d;  in clk_wzrd_get_divisors_ver()
362 						divider->o = o;  in clk_wzrd_get_divisors_ver()
375 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_get_divisors()  local
398 						divider->m = m;  in clk_wzrd_get_divisors()
399 						divider->d = d;  in clk_wzrd_get_divisors()
400 						divider->o = o;  in clk_wzrd_get_divisors()
410 static int clk_wzrd_reconfig(struct clk_wzrd_divider *divider, void __iomem *div_addr)  in clk_wzrd_reconfig()  argument
416 	err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,  in clk_wzrd_reconfig()
425 	return readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,  in clk_wzrd_reconfig()
434 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_ver_all_nolock()  local
442 	writel(0, divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_4));  in clk_wzrd_dynamic_ver_all_nolock()
444 	m = divider->m;  in clk_wzrd_dynamic_ver_all_nolock()
447 	regval1 = readl(divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
455 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
458 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
461 	value2 = divider->d;  in clk_wzrd_dynamic_ver_all_nolock()
465 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
468 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1, WZRD_DIVCLK));  in clk_wzrd_dynamic_ver_all_nolock()
470 	value = divider->o;  in clk_wzrd_dynamic_ver_all_nolock()
472 	regval1 = readl(divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
486 	writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
489 	writel(regval, divider->base + WZRD_CLK_CFG_REG(1,  in clk_wzrd_dynamic_ver_all_nolock()
491 	div_addr = divider->base + WZRD_DR_INIT_VERSAL_OFFSET;  in clk_wzrd_dynamic_ver_all_nolock()
493 	return clk_wzrd_reconfig(divider, div_addr);  in clk_wzrd_dynamic_ver_all_nolock()
499 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_all_nolock()  local
501 	void __iomem *div_addr = divider->base;  in clk_wzrd_dynamic_all_nolock()
509 	vco_freq = DIV_ROUND_CLOSEST(parent_rate * divider->m, divider->d);  in clk_wzrd_dynamic_all_nolock()
521 	writel(reg, divider->base + WZRD_CLK_CFG_REG(0, 2));  in clk_wzrd_dynamic_all_nolock()
523 	reg = FIELD_PREP(WZRD_CLKFBOUT_MULT_MASK, divider->m) |  in clk_wzrd_dynamic_all_nolock()
524 	      FIELD_PREP(WZRD_DIVCLK_DIVIDE_MASK, divider->d);  in clk_wzrd_dynamic_all_nolock()
525 	writel(reg, divider->base + WZRD_CLK_CFG_REG(0, 0));  in clk_wzrd_dynamic_all_nolock()
526 	writel(divider->o, divider->base + WZRD_CLK_CFG_REG(0, 2));  in clk_wzrd_dynamic_all_nolock()
527 	writel(0, divider->base + WZRD_CLK_CFG_REG(0, 3));  in clk_wzrd_dynamic_all_nolock()
528 	div_addr = divider->base + WZRD_DR_INIT_REG_OFFSET;  in clk_wzrd_dynamic_all_nolock()
529 	return clk_wzrd_reconfig(divider, div_addr);  in clk_wzrd_dynamic_all_nolock()
535 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_all()  local
539 	spin_lock_irqsave(divider->lock, flags);  in clk_wzrd_dynamic_all()
543 	spin_unlock_irqrestore(divider->lock, flags);  in clk_wzrd_dynamic_all()
551 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_all_ver()  local
555 	spin_lock_irqsave(divider->lock, flags);  in clk_wzrd_dynamic_all_ver()
559 	spin_unlock_irqrestore(divider->lock, flags);  in clk_wzrd_dynamic_all_ver()
567 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_recalc_rate_all()  local
570 	reg = readl(divider->base + WZRD_CLK_CFG_REG(0, 0));  in clk_wzrd_recalc_rate_all()
573 	reg = readl(divider->base + WZRD_CLK_CFG_REG(0, 2));  in clk_wzrd_recalc_rate_all()
578 	return divider_recalc_rate(hw, parent_rate * m, div, divider->table,  in clk_wzrd_recalc_rate_all()
579 		divider->flags, divider->width);  in clk_wzrd_recalc_rate_all()
585 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_recalc_rate_all_ver()  local
589 	edge = !!(readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_1)) &  in clk_wzrd_recalc_rate_all_ver()
592 	reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_2));  in clk_wzrd_recalc_rate_all_ver()
600 	regl = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_4)) &  in clk_wzrd_recalc_rate_all_ver()
603 		regl = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_3))  in clk_wzrd_recalc_rate_all_ver()
612 	reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKOUT0_1));  in clk_wzrd_recalc_rate_all_ver()
617 	reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKOUT0_2));  in clk_wzrd_recalc_rate_all_ver()
632 	edged = !!(readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_DESKEW_2)) &  in clk_wzrd_recalc_rate_all_ver()
634 	reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_DIVCLK));  in clk_wzrd_recalc_rate_all_ver()
644 	return divider_recalc_rate(hw, parent_rate, div, divider->table,  in clk_wzrd_recalc_rate_all_ver()
645 			divider->flags, divider->width);  in clk_wzrd_recalc_rate_all_ver()
651 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_round_rate_all()  local
660 	m = divider->m;  in clk_wzrd_round_rate_all()
661 	d = divider->d;  in clk_wzrd_round_rate_all()
662 	o = divider->o;  in clk_wzrd_round_rate_all()
665 	int_freq =  divider_recalc_rate(hw, *prate * m, div, divider->table,  in clk_wzrd_round_rate_all()
666 					divider->flags, divider->width);  in clk_wzrd_round_rate_all()
704 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_recalc_ratef()  local
705 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_recalc_ratef()
708 	div = val & div_mask(divider->width);  in clk_wzrd_recalc_ratef()
720 	struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);  in clk_wzrd_dynamic_reconfig_f()  local
721 	void __iomem *div_addr = divider->base + divider->offset;  in clk_wzrd_dynamic_reconfig_f()
738 	err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,  in clk_wzrd_dynamic_reconfig_f()
746 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_reconfig_f()
748 	       divider->base + WZRD_DR_INIT_REG_OFFSET);  in clk_wzrd_dynamic_reconfig_f()
751 	return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,  in clk_wzrd_dynamic_reconfig_f()
1137 		dev_err(&pdev->dev, "unable to register divider clock\n");  in clk_wzrd_probe()
1186 				"unable to register divider clock\n");  in clk_wzrd_probe()