clk/uniphier/clk-uniphier-sys.c

24 	UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4),		\
40 	UNIPHIER_CLK_FACTOR("nand-4x", (idx), "nand", 4, 1)
87 	UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1),		/* 1597.44 MHz */
88 	UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512),	/* 288 MHz */
89 	UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1),		/* 589.824 MHz */
90 	UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512),	/* 270 MHz */
103 	UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1),		/* 1600 MHz */
104 	UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25),	/* 288 MHz */
105 	UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125),	/* 589.824 MHz */
106 	UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25),	/* 270 MHz */
107 	UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1),		/* 250 MHz */
132 	UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1),		/* 1600 MHz */
133 	UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25),	/* 288 MHz */
134 	UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25),	/* 270 MHz */
147 	UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1),		/* 2400 MHz */
148 	UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1),	/* 2560 MHz */
149 	UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125),	/* 2949.12 MHz */
166 	UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1),		/* 2400 MHz */
190 	UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 392, 5),		/* 1960 MHz */
191 	UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1),		/* 1600 MHz */
192 	UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1),		/* 2000 MHz */
193 	UNIPHIER_CLK_FACTOR("vspll", -1, "ref", 80, 1),		/* 2000 MHz */
199 	UNIPHIER_LD11_SYS_CLK_EMMC(4),
209 	UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
210 	UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8),
211 	UNIPHIER_CLK_DIV3("spll", 3, 4, 8),
212 	/* Note: both gear1 and gear4 are spll/4.  This is not a bug. */
214 			     "cpll/2", "spll/4", "cpll/3", "spll/3",
215 			     "spll/4", "spll/8", "cpll/4", "cpll/8"),
217 			     "mpll/2", "spll/4", "mpll/3", "spll/3",
218 			     "spll/4", "spll/8", "mpll/4", "mpll/8"),
223 	UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 88, 1),		/* ARM: 2200 MHz */
224 	UNIPHIER_CLK_FACTOR("gppll", -1, "ref", 52, 1),		/* Mali: 1300 MHz */
225 	UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1),		/* Codec: 1600 MHz */
226 	UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1),		/* 2000 MHz */
227 	UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1),		/* IPP: 2200 MHz */
228 	UNIPHIER_CLK_FACTOR("vppll", -1, "ref", 504, 5),	/* 2520 MHz */
234 	UNIPHIER_LD11_SYS_CLK_EMMC(4),
250 	UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 4),
255 	UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
256 	UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
257 	UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8),
260 			     "spll/4", "spll/8", "cpll/4", "cpll/8"),
263 			     "spll/4", "spll/8", "cpll/4", "cpll/8"),
266 			     "spll/4", "spll/8", "s2pll/4", "s2pll/8"),
271 	UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 104, 1),		/* ARM: 2600 MHz */
272 	UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1),		/* 2000 MHz */
273 	UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1),		/* IPP: 2400 MHz */
280 	UNIPHIER_LD11_SYS_CLK_EMMC(4),
283 	UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x210c, 4),	/* =GIO0 */
298 	UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
299 	UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
300 	UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8),
303 			     "spll/4", "spll/8", "cpll/4", "cpll/8"),
306 			     "spll/4", "spll/8", "s2pll/4", "s2pll/8"),
311 	UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 100, 1),		/* ARM: 2500 MHz */
312 	UNIPHIER_CLK_FACTOR("spll", -1, "ref", 32, 1),		/* 800 MHz */
316 	UNIPHIER_CLK_GATE("emmc", 4, NULL, 0x2108, 8),
327 	UNIPHIER_CLK_DIV5("cpll", 2, 4, 8, 16, 32),
329 			     "cpll/2", "cpll/4", "cpll/8", "cpll/16",
335 	UNIPHIER_CLK_DIV("gpll", 4),
341 			.parent_names = { "gpll/4", "ref", },