Lines Matching +full:fixed +full:- +full:parent +full:- +full:rate

1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
76 * @rate: input frequency from source
77 * @max_rate: max rate allowed
81 unsigned long rate; member
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
108 * flag indicates that this divider is for fixed rate PLL.
109 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
112 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
154 * struct tegra_clk_pll_freq_table - PLL frequecy table
156 * @input_rate: input rate from source
157 * @output_rate: output rate from PLL for the input rate
175 * struct pdiv_map - map post divider to hw value
186 * struct div_nmp - offset and width of m,n and p fields
215 * struct tegra_clk_pll_params - PLL parameters
252 * @fixed_rate: PLL rate if it is fixed
253 * @mdiv_default: Default value for fixed mdiv for this PLL
265 * time the rate is changed while the PLL is
270 * PLL's rate.
272 * PLL's rate.
275 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
277 * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
279 * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
281 * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
283 * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
285 * TEGRA_PLLM - PLLM has additional override settings in PMC. This
287 * TEGRA_PLL_FIXED - We are not supposed to change output frequency
289 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
290 * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
292 * TEGRA_PLL_BYPASS - PLL has bypass bit
293 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
294 * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv
296 * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This
298 * TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output
343 unsigned long rate, unsigned long parent_rate);
369 * struct tegra_clk_pll - Tegra PLL clock
371 * @hw: handle between common and hardware-specifix interfaces
388 * struct tegra_audio_clk_info - Tegra Audio Clk Information
393 * @parent: name of the parent of the audio pll
399 char *parent; member
497 * struct tegra_clk_pll_out - PLL divider down clock
499 * @hw: handle between common and hardware-specific interfaces
504 * @flags: hardware-specific flags
524 * struct tegra_clk_periph_regs - Registers controlling peripheral clock
543 * struct tegra_clk_periph_gate - peripheral gate clock
546 * @hw: handle between common and hardware-specific interfaces
549 * @flags: hardware-specific flags
554 * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed
556 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
559 * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
597 const char *parent,
605 * struct clk-periph - peripheral clock
608 * @hw: handle between common and hardware-specific interfaces
711 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \
720 * struct clk_super_mux - super clock
722 * @hw: handle between common and hardware-specific interfaces
725 * @flags: hardware-specific flags
726 * @div2_index: bit controlling divide-by-2
727 * @pllx_index: PLLX index in the parent list
731 * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
733 * TEGRA210_CPU_CLK - This flag is used to identify CPU cluster for gen5
734 * super mux parent using PLLP branches. To use PLLP branches to CPU, need
736 * TEGRA20_SUPER_CLK - Tegra20 doesn't have a dedicated divider for Super
737 * clocks, it only has a clock-skipper.
774 * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
776 * @hw: handle between common and hardware-specific interfaces
778 * @flags: hardware-specific flags
799 * struct clk_init_table - clock initialization table
801 * @parent_id: parent clock id as mentioned in device tree bindings
802 * @rate: rate to set
808 unsigned long rate; member
813 * struct clk_duplicate - duplicate clocks
909 int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,