1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
17 #include <soc/starfive/reset-starfive-jh71x0.h>
19 #include <dt-bindings/clock/starfive,jh7110-crg.h>
21 #include "clk-starfive-jh7110.h"
140 	/* vdec */
329 	unsigned int idx = clkspec->args[0];  in jh7110_sysclk_get()
332 		return &priv->reg[idx].hw;  in jh7110_sysclk_get()
334 	return ERR_PTR(-EINVAL);  in jh7110_sysclk_get()
363 		return -ENOMEM;  in jh7110_reset_controller_register()
365 	rdev->base = priv->base;  in jh7110_reset_controller_register()
367 	adev = &rdev->adev;  in jh7110_reset_controller_register()
368 	adev->name = adev_name;  in jh7110_reset_controller_register()
369 	adev->dev.parent = priv->dev;  in jh7110_reset_controller_register()
370 	adev->dev.release = jh7110_reset_adev_release;  in jh7110_reset_controller_register()
371 	adev->id = adev_id;  in jh7110_reset_controller_register()
383 	return devm_add_action_or_reset(priv->dev,  in jh7110_reset_controller_register()
395 	priv = devm_kzalloc(&pdev->dev,  in jh7110_syscrg_probe()
399 		return -ENOMEM;  in jh7110_syscrg_probe()
401 	spin_lock_init(&priv->rmw_lock);  in jh7110_syscrg_probe()
402 	priv->dev = &pdev->dev;  in jh7110_syscrg_probe()
403 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in jh7110_syscrg_probe()
404 	if (IS_ERR(priv->base))  in jh7110_syscrg_probe()
405 		return PTR_ERR(priv->base);  in jh7110_syscrg_probe()
408 	pllclk = clk_get(priv->dev, "pll0_out");  in jh7110_syscrg_probe()
410 		/* 24MHz -> 1000.0MHz */  in jh7110_syscrg_probe()
411 		priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",  in jh7110_syscrg_probe()
413 		if (IS_ERR(priv->pll[0]))  in jh7110_syscrg_probe()
414 			return PTR_ERR(priv->pll[0]);  in jh7110_syscrg_probe()
417 		priv->pll[0] = NULL;  in jh7110_syscrg_probe()
420 	pllclk = clk_get(priv->dev, "pll1_out");  in jh7110_syscrg_probe()
422 		/* 24MHz -> 1066.0MHz */  in jh7110_syscrg_probe()
423 		priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",  in jh7110_syscrg_probe()
425 		if (IS_ERR(priv->pll[1]))  in jh7110_syscrg_probe()
426 			return PTR_ERR(priv->pll[1]);  in jh7110_syscrg_probe()
429 		priv->pll[1] = NULL;  in jh7110_syscrg_probe()
432 	pllclk = clk_get(priv->dev, "pll2_out");  in jh7110_syscrg_probe()
434 		/* 24MHz -> 1188.0MHz */  in jh7110_syscrg_probe()
435 		priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",  in jh7110_syscrg_probe()
437 		if (IS_ERR(priv->pll[2]))  in jh7110_syscrg_probe()
438 			return PTR_ERR(priv->pll[2]);  in jh7110_syscrg_probe()
441 		priv->pll[2] = NULL;  in jh7110_syscrg_probe()
455 		struct jh71x0_clk *clk = &priv->reg[idx];  in jh7110_syscrg_probe()
462 				parents[i].hw = &priv->reg[pidx].hw;  in jh7110_syscrg_probe()
481 			else if (pidx == JH7110_SYSCLK_PLL0_OUT && !priv->pll[0])  in jh7110_syscrg_probe()
483 			else if (pidx == JH7110_SYSCLK_PLL1_OUT && !priv->pll[1])  in jh7110_syscrg_probe()
485 			else if (pidx == JH7110_SYSCLK_PLL2_OUT && !priv->pll[2])  in jh7110_syscrg_probe()
488 				parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT];  in jh7110_syscrg_probe()
491 		clk->hw.init = &init;  in jh7110_syscrg_probe()
492 		clk->idx = idx;  in jh7110_syscrg_probe()
493 		clk->max_div = max & JH71X0_CLK_DIV_MASK;  in jh7110_syscrg_probe()
495 		ret = devm_clk_hw_register(&pdev->dev, &clk->hw);  in jh7110_syscrg_probe()
500 	ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_sysclk_get, priv);  in jh7110_syscrg_probe()
504 	return jh7110_reset_controller_register(priv, "rst-sys", 0);  in jh7110_syscrg_probe()
508 	{ .compatible = "starfive,jh7110-syscrg" },
514 		.name = "clk-starfive-jh7110-sys",