Lines Matching full:parents
446 struct clk_parent_data parents[4] = {}; in jh7110_syscrg_probe() local
450 .parent_data = parents, in jh7110_syscrg_probe()
459 unsigned int pidx = jh7110_sysclk_data[idx].parents[i]; in jh7110_syscrg_probe()
462 parents[i].hw = &priv->reg[pidx].hw; in jh7110_syscrg_probe()
464 parents[i].fw_name = "osc"; in jh7110_syscrg_probe()
466 parents[i].fw_name = "gmac1_rmii_refin"; in jh7110_syscrg_probe()
468 parents[i].fw_name = "gmac1_rgmii_rxin"; in jh7110_syscrg_probe()
470 parents[i].fw_name = "i2stx_bclk_ext"; in jh7110_syscrg_probe()
472 parents[i].fw_name = "i2stx_lrck_ext"; in jh7110_syscrg_probe()
474 parents[i].fw_name = "i2srx_bclk_ext"; in jh7110_syscrg_probe()
476 parents[i].fw_name = "i2srx_lrck_ext"; in jh7110_syscrg_probe()
478 parents[i].fw_name = "tdm_ext"; in jh7110_syscrg_probe()
480 parents[i].fw_name = "mclk_ext"; in jh7110_syscrg_probe()
482 parents[i].fw_name = "pll0_out"; in jh7110_syscrg_probe()
484 parents[i].fw_name = "pll1_out"; in jh7110_syscrg_probe()
486 parents[i].fw_name = "pll2_out"; in jh7110_syscrg_probe()
488 parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT]; in jh7110_syscrg_probe()