Lines Matching +full:pd +full:- +full:disable
1 // SPDX-License-Identifier: GPL-2.0
12 #include "sifive-prci.h"
13 #include "fu540-prci.h"
14 #include "fu740-prci.h"
21 * __prci_readl() - read from a PRCI register
22 * @pd: PRCI context
26 * address of the PRCI register target described by @pd, and return
31 * Return: the contents of the register described by @pd and @offs.
33 static u32 __prci_readl(struct __prci_data *pd, u32 offs) in __prci_readl() argument
35 return readl_relaxed(pd->va + offs); in __prci_readl()
38 static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd) in __prci_writel() argument
40 writel_relaxed(v, pd->va + offs); in __prci_writel()
43 /* WRPLL-related private functions */
46 * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
65 c->divr = v; in __prci_wrpll_unpack()
69 c->divf = v; in __prci_wrpll_unpack()
73 c->divq = v; in __prci_wrpll_unpack()
77 c->range = v; in __prci_wrpll_unpack()
79 c->flags &= in __prci_wrpll_unpack()
83 c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK; in __prci_wrpll_unpack()
87 * __prci_wrpll_pack() - pack PLL configuration parameters into a register value
105 r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT; in __prci_wrpll_pack()
106 r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT; in __prci_wrpll_pack()
107 r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT; in __prci_wrpll_pack()
108 r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT; in __prci_wrpll_pack()
117 * __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI
118 * @pd: PRCI context
122 * the PRCI identified by @pd, and store it into the local configuration
126 * @pd and @pwd from changing during execution.
128 static void __prci_wrpll_read_cfg0(struct __prci_data *pd, in __prci_wrpll_read_cfg0() argument
131 __prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs)); in __prci_wrpll_read_cfg0()
135 * __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI
136 * @pd: PRCI context
146 * @pd and @pwd from changing during execution.
148 static void __prci_wrpll_write_cfg0(struct __prci_data *pd, in __prci_wrpll_write_cfg0() argument
152 __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd); in __prci_wrpll_write_cfg0()
154 memcpy(&pwd->c, c, sizeof(*c)); in __prci_wrpll_write_cfg0()
158 * __prci_wrpll_write_cfg1() - write Clock enable/disable configuration
160 * @pd: PRCI context
162 * @enable: Clock enable or disable value
164 static void __prci_wrpll_write_cfg1(struct __prci_data *pd, in __prci_wrpll_write_cfg1() argument
168 __prci_writel(enable, pwd->cfg1_offs, pd); in __prci_wrpll_write_cfg1()
182 struct __prci_wrpll_data *pwd = pc->pwd; in sifive_prci_wrpll_recalc_rate()
184 return wrpll_calc_output_rate(&pwd->c, parent_rate); in sifive_prci_wrpll_recalc_rate()
192 struct __prci_wrpll_data *pwd = pc->pwd; in sifive_prci_wrpll_round_rate()
195 memcpy(&c, &pwd->c, sizeof(c)); in sifive_prci_wrpll_round_rate()
206 struct __prci_wrpll_data *pwd = pc->pwd; in sifive_prci_wrpll_set_rate()
207 struct __prci_data *pd = pc->pd; in sifive_prci_wrpll_set_rate() local
210 r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate); in sifive_prci_wrpll_set_rate()
214 if (pwd->enable_bypass) in sifive_prci_wrpll_set_rate()
215 pwd->enable_bypass(pd); in sifive_prci_wrpll_set_rate()
217 __prci_wrpll_write_cfg0(pd, pwd, &pwd->c); in sifive_prci_wrpll_set_rate()
219 udelay(wrpll_calc_max_lock_us(&pwd->c)); in sifive_prci_wrpll_set_rate()
227 struct __prci_wrpll_data *pwd = pc->pwd; in sifive_clk_is_enabled()
228 struct __prci_data *pd = pc->pd; in sifive_clk_is_enabled() local
231 r = __prci_readl(pd, pwd->cfg1_offs); in sifive_clk_is_enabled()
242 struct __prci_wrpll_data *pwd = pc->pwd; in sifive_prci_clock_enable()
243 struct __prci_data *pd = pc->pd; in sifive_prci_clock_enable() local
248 __prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK); in sifive_prci_clock_enable()
250 if (pwd->disable_bypass) in sifive_prci_clock_enable()
251 pwd->disable_bypass(pd); in sifive_prci_clock_enable()
259 struct __prci_wrpll_data *pwd = pc->pwd; in sifive_prci_clock_disable()
260 struct __prci_data *pd = pc->pd; in sifive_prci_clock_disable() local
263 if (pwd->enable_bypass) in sifive_prci_clock_disable()
264 pwd->enable_bypass(pd); in sifive_prci_clock_disable()
266 r = __prci_readl(pd, pwd->cfg1_offs); in sifive_prci_clock_disable()
269 __prci_wrpll_write_cfg1(pd, pwd, r); in sifive_prci_clock_disable()
278 struct __prci_data *pd = pc->pd; in sifive_prci_tlclksel_recalc_rate() local
282 v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET); in sifive_prci_tlclksel_recalc_rate()
295 struct __prci_data *pd = pc->pd; in sifive_prci_hfpclkplldiv_recalc_rate() local
296 u32 div = __prci_readl(pd, PRCI_HFPCLKPLLDIV_OFFSET); in sifive_prci_hfpclkplldiv_recalc_rate()
306 * sifive_prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
307 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
314 void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd) in sifive_prci_coreclksel_use_hfclk() argument
318 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); in sifive_prci_coreclksel_use_hfclk()
320 __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); in sifive_prci_coreclksel_use_hfclk()
322 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ in sifive_prci_coreclksel_use_hfclk()
326 * sifive_prci_coreclksel_use_corepll() - switch the CORECLK mux to output
328 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
335 void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd) in sifive_prci_coreclksel_use_corepll() argument
339 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); in sifive_prci_coreclksel_use_corepll()
341 __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); in sifive_prci_coreclksel_use_corepll()
343 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ in sifive_prci_coreclksel_use_corepll()
347 * sifive_prci_coreclksel_use_final_corepll() - switch the CORECLK mux to output
349 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
357 void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd) in sifive_prci_coreclksel_use_final_corepll() argument
361 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); in sifive_prci_coreclksel_use_final_corepll()
363 __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); in sifive_prci_coreclksel_use_final_corepll()
365 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ in sifive_prci_coreclksel_use_final_corepll()
369 * sifive_prci_corepllsel_use_dvfscorepll() - switch the COREPLL mux to
371 * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
378 void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd) in sifive_prci_corepllsel_use_dvfscorepll() argument
382 r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); in sifive_prci_corepllsel_use_dvfscorepll()
384 __prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd); in sifive_prci_corepllsel_use_dvfscorepll()
386 r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */ in sifive_prci_corepllsel_use_dvfscorepll()
390 * sifive_prci_corepllsel_use_corepll() - switch the COREPLL mux to
392 * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
399 void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd) in sifive_prci_corepllsel_use_corepll() argument
403 r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); in sifive_prci_corepllsel_use_corepll()
405 __prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd); in sifive_prci_corepllsel_use_corepll()
407 r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */ in sifive_prci_corepllsel_use_corepll()
411 * sifive_prci_hfpclkpllsel_use_hfclk() - switch the HFPCLKPLL mux to
413 * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
420 void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd) in sifive_prci_hfpclkpllsel_use_hfclk() argument
424 r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); in sifive_prci_hfpclkpllsel_use_hfclk()
426 __prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd); in sifive_prci_hfpclkpllsel_use_hfclk()
428 r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */ in sifive_prci_hfpclkpllsel_use_hfclk()
432 * sifive_prci_hfpclkpllsel_use_hfpclkpll() - switch the HFPCLKPLL mux to
434 * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
441 void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd) in sifive_prci_hfpclkpllsel_use_hfpclkpll() argument
445 r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); in sifive_prci_hfpclkpllsel_use_hfpclkpll()
447 __prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd); in sifive_prci_hfpclkpllsel_use_hfpclkpll()
449 r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */ in sifive_prci_hfpclkpllsel_use_hfpclkpll()
452 /* PCIE AUX clock APIs for enable, disable. */
456 struct __prci_data *pd = pc->pd; in sifive_prci_pcie_aux_clock_is_enabled() local
459 r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); in sifive_prci_pcie_aux_clock_is_enabled()
470 struct __prci_data *pd = pc->pd; in sifive_prci_pcie_aux_clock_enable() local
476 __prci_writel(1, PRCI_PCIE_AUX_OFFSET, pd); in sifive_prci_pcie_aux_clock_enable()
477 r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); /* barrier */ in sifive_prci_pcie_aux_clock_enable()
485 struct __prci_data *pd = pc->pd; in sifive_prci_pcie_aux_clock_disable() local
488 __prci_writel(0, PRCI_PCIE_AUX_OFFSET, pd); in sifive_prci_pcie_aux_clock_disable()
489 r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); /* barrier */ in sifive_prci_pcie_aux_clock_disable()
494 * __prci_register_clocks() - register clock controls in the PRCI
496 * @pd: The pointer for PRCI per-device instance data
504 static int __prci_register_clocks(struct device *dev, struct __prci_data *pd, in __prci_register_clocks() argument
511 parent_count = of_clk_get_parent_count(dev->of_node); in __prci_register_clocks()
515 return -EINVAL; in __prci_register_clocks()
519 for (i = 0; i < desc->num_clks; ++i) { in __prci_register_clocks()
520 pic = &(desc->clks[i]); in __prci_register_clocks()
522 init.name = pic->name; in __prci_register_clocks()
523 init.parent_names = &pic->parent_name; in __prci_register_clocks()
525 init.ops = pic->ops; in __prci_register_clocks()
526 pic->hw.init = &init; in __prci_register_clocks()
528 pic->pd = pd; in __prci_register_clocks()
530 if (pic->pwd) in __prci_register_clocks()
531 __prci_wrpll_read_cfg0(pd, pic->pwd); in __prci_register_clocks()
533 r = devm_clk_hw_register(dev, &pic->hw); in __prci_register_clocks()
540 r = clk_hw_register_clkdev(&pic->hw, pic->name, dev_name(dev)); in __prci_register_clocks()
547 pd->hw_clks.hws[i] = &pic->hw; in __prci_register_clocks()
550 pd->hw_clks.num = i; in __prci_register_clocks()
553 &pd->hw_clks); in __prci_register_clocks()
563 * sifive_prci_probe() - initialize prci data and check parent count
570 struct device *dev = &pdev->dev; in sifive_prci_probe()
571 struct __prci_data *pd; in sifive_prci_probe() local
575 desc = of_device_get_match_data(&pdev->dev); in sifive_prci_probe()
577 pd = devm_kzalloc(dev, struct_size(pd, hw_clks.hws, desc->num_clks), GFP_KERNEL); in sifive_prci_probe()
578 if (!pd) in sifive_prci_probe()
579 return -ENOMEM; in sifive_prci_probe()
581 pd->va = devm_platform_ioremap_resource(pdev, 0); in sifive_prci_probe()
582 if (IS_ERR(pd->va)) in sifive_prci_probe()
583 return PTR_ERR(pd->va); in sifive_prci_probe()
585 pd->reset.rcdev.owner = THIS_MODULE; in sifive_prci_probe()
586 pd->reset.rcdev.nr_resets = PRCI_RST_NR; in sifive_prci_probe()
587 pd->reset.rcdev.ops = &reset_simple_ops; in sifive_prci_probe()
588 pd->reset.rcdev.of_node = pdev->dev.of_node; in sifive_prci_probe()
589 pd->reset.active_low = true; in sifive_prci_probe()
590 pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET; in sifive_prci_probe()
591 spin_lock_init(&pd->reset.lock); in sifive_prci_probe()
593 r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev); in sifive_prci_probe()
598 r = __prci_register_clocks(dev, pd, desc); in sifive_prci_probe()
610 {.compatible = "sifive,fu540-c000-prci", .data = &prci_clk_fu540},
611 {.compatible = "sifive,fu740-c000-prci", .data = &prci_clk_fu740},
617 .name = "sifive-clk-prci",