22  * @pd: PRCI context
26  * address of the PRCI register target described by @pd, and return
31  * Return: the contents of the register described by @pd and @offs.
33 static u32 __prci_readl(struct __prci_data *pd, u32 offs)  in __prci_readl()  argument
35 	return readl_relaxed(pd->va + offs);  in __prci_readl()
38 static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)  in __prci_writel()  argument
40 	writel_relaxed(v, pd->va + offs);  in __prci_writel()
118  * @pd: PRCI context
122  * the PRCI identified by @pd, and store it into the local configuration
126  *          @pd and @pwd from changing during execution.
128 static void __prci_wrpll_read_cfg0(struct __prci_data *pd,  in __prci_wrpll_read_cfg0()  argument
131 	__prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));  in __prci_wrpll_read_cfg0()
136  * @pd: PRCI context
146  *          @pd and @pwd from changing during execution.
148 static void __prci_wrpll_write_cfg0(struct __prci_data *pd,  in __prci_wrpll_write_cfg0()  argument
152 	__prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);  in __prci_wrpll_write_cfg0()
160  * @pd: PRCI context
164 static void __prci_wrpll_write_cfg1(struct __prci_data *pd,  in __prci_wrpll_write_cfg1()  argument
168 	__prci_writel(enable, pwd->cfg1_offs, pd);  in __prci_wrpll_write_cfg1()
207 	struct __prci_data *pd = pc->pd;  in sifive_prci_wrpll_set_rate()  local
215 		pwd->enable_bypass(pd);  in sifive_prci_wrpll_set_rate()
217 	__prci_wrpll_write_cfg0(pd, pwd, &pwd->c);  in sifive_prci_wrpll_set_rate()
228 	struct __prci_data *pd = pc->pd;  in sifive_clk_is_enabled()  local
231 	r = __prci_readl(pd, pwd->cfg1_offs);  in sifive_clk_is_enabled()
243 	struct __prci_data *pd = pc->pd;  in sifive_prci_clock_enable()  local
248 	__prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK);  in sifive_prci_clock_enable()
251 		pwd->disable_bypass(pd);  in sifive_prci_clock_enable()
260 	struct __prci_data *pd = pc->pd;  in sifive_prci_clock_disable()  local
264 		pwd->enable_bypass(pd);  in sifive_prci_clock_disable()
266 	r = __prci_readl(pd, pwd->cfg1_offs);  in sifive_prci_clock_disable()
269 	__prci_wrpll_write_cfg1(pd, pwd, r);  in sifive_prci_clock_disable()
278 	struct __prci_data *pd = pc->pd;  in sifive_prci_tlclksel_recalc_rate()  local
282 	v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);  in sifive_prci_tlclksel_recalc_rate()
295 	struct __prci_data *pd = pc->pd;  in sifive_prci_hfpclkplldiv_recalc_rate()  local
296 	u32 div = __prci_readl(pd, PRCI_HFPCLKPLLDIV_OFFSET);  in sifive_prci_hfpclkplldiv_recalc_rate()
307  * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
314 void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd)  in sifive_prci_coreclksel_use_hfclk()  argument
318 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);  in sifive_prci_coreclksel_use_hfclk()
320 	__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);  in sifive_prci_coreclksel_use_hfclk()
322 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);	/* barrier */  in sifive_prci_coreclksel_use_hfclk()
328  * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
335 void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd)  in sifive_prci_coreclksel_use_corepll()  argument
339 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);  in sifive_prci_coreclksel_use_corepll()
341 	__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);  in sifive_prci_coreclksel_use_corepll()
343 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);	/* barrier */  in sifive_prci_coreclksel_use_corepll()
349  * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
357 void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd)  in sifive_prci_coreclksel_use_final_corepll()  argument
361 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);  in sifive_prci_coreclksel_use_final_corepll()
363 	__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);  in sifive_prci_coreclksel_use_final_corepll()
365 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);	/* barrier */  in sifive_prci_coreclksel_use_final_corepll()
371  * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
378 void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd)  in sifive_prci_corepllsel_use_dvfscorepll()  argument
382 	r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);  in sifive_prci_corepllsel_use_dvfscorepll()
384 	__prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd);  in sifive_prci_corepllsel_use_dvfscorepll()
386 	r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);	/* barrier */  in sifive_prci_corepllsel_use_dvfscorepll()
392  * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
399 void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd)  in sifive_prci_corepllsel_use_corepll()  argument
403 	r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);  in sifive_prci_corepllsel_use_corepll()
405 	__prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd);  in sifive_prci_corepllsel_use_corepll()
407 	r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);	/* barrier */  in sifive_prci_corepllsel_use_corepll()
413  * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
420 void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd)  in sifive_prci_hfpclkpllsel_use_hfclk()  argument
424 	r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);  in sifive_prci_hfpclkpllsel_use_hfclk()
426 	__prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd);  in sifive_prci_hfpclkpllsel_use_hfclk()
428 	r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);	/* barrier */  in sifive_prci_hfpclkpllsel_use_hfclk()
434  * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
441 void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd)  in sifive_prci_hfpclkpllsel_use_hfpclkpll()  argument
445 	r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);  in sifive_prci_hfpclkpllsel_use_hfpclkpll()
447 	__prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd);  in sifive_prci_hfpclkpllsel_use_hfpclkpll()
449 	r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);	/* barrier */  in sifive_prci_hfpclkpllsel_use_hfpclkpll()
456 	struct __prci_data *pd = pc->pd;  in sifive_prci_pcie_aux_clock_is_enabled()  local
459 	r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET);  in sifive_prci_pcie_aux_clock_is_enabled()
470 	struct __prci_data *pd = pc->pd;  in sifive_prci_pcie_aux_clock_enable()  local
476 	__prci_writel(1, PRCI_PCIE_AUX_OFFSET, pd);  in sifive_prci_pcie_aux_clock_enable()
477 	r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET);	/* barrier */  in sifive_prci_pcie_aux_clock_enable()
485 	struct __prci_data *pd = pc->pd;  in sifive_prci_pcie_aux_clock_disable()  local
488 	__prci_writel(0, PRCI_PCIE_AUX_OFFSET, pd);  in sifive_prci_pcie_aux_clock_disable()
489 	r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET);	/* barrier */  in sifive_prci_pcie_aux_clock_disable()
496  * @pd: The pointer for PRCI per-device instance data
504 static int __prci_register_clocks(struct device *dev, struct __prci_data *pd,  in __prci_register_clocks()  argument
528 		pic->pd = pd;  in __prci_register_clocks()
531 			__prci_wrpll_read_cfg0(pd, pic->pwd);  in __prci_register_clocks()
547 		pd->hw_clks.hws[i] = &pic->hw;  in __prci_register_clocks()
550 	pd->hw_clks.num = i;  in __prci_register_clocks()
553 					&pd->hw_clks);  in __prci_register_clocks()
571 	struct __prci_data *pd;  in sifive_prci_probe()  local
577 	pd = devm_kzalloc(dev, struct_size(pd, hw_clks.hws, desc->num_clks), GFP_KERNEL);  in sifive_prci_probe()
578 	if (!pd)  in sifive_prci_probe()
581 	pd->va = devm_platform_ioremap_resource(pdev, 0);  in sifive_prci_probe()
582 	if (IS_ERR(pd->va))  in sifive_prci_probe()
583 		return PTR_ERR(pd->va);  in sifive_prci_probe()
585 	pd->reset.rcdev.owner = THIS_MODULE;  in sifive_prci_probe()
586 	pd->reset.rcdev.nr_resets = PRCI_RST_NR;  in sifive_prci_probe()
587 	pd->reset.rcdev.ops = &reset_simple_ops;  in sifive_prci_probe()
588 	pd->reset.rcdev.of_node = pdev->dev.of_node;  in sifive_prci_probe()
589 	pd->reset.active_low = true;  in sifive_prci_probe()
590 	pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET;  in sifive_prci_probe()
591 	spin_lock_init(&pd->reset.lock);  in sifive_prci_probe()
593 	r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev);  in sifive_prci_probe()
598 	r = __prci_register_clocks(dev, pd, desc);  in sifive_prci_probe()