Lines Matching full:gate
1262 GATE(CLK_GOUT_CMU_BUS0_BOOST, "gout_cmu_bus0_boost",
1264 GATE(CLK_GOUT_CMU_BUS1_BOOST, "gout_cmu_bus1_boost",
1266 GATE(CLK_GOUT_CMU_BUS2_BOOST, "gout_cmu_bus2_boost",
1268 GATE(CLK_GOUT_CMU_CORE_BOOST, "gout_cmu_core_boost",
1270 GATE(CLK_GOUT_CMU_CPUCL0_BOOST, "gout_cmu_cpucl0_boost",
1273 GATE(CLK_GOUT_CMU_CPUCL1_BOOST, "gout_cmu_cpucl1_boost",
1276 GATE(CLK_GOUT_CMU_CPUCL2_BOOST, "gout_cmu_cpucl2_boost",
1279 GATE(CLK_GOUT_CMU_MIF_BOOST, "gout_cmu_mif_boost",
1282 GATE(CLK_GOUT_CMU_MIF_SWITCH, "gout_cmu_mif_switch",
1284 GATE(CLK_GOUT_CMU_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus",
1286 GATE(CLK_GOUT_CMU_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
1288 GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
1290 GATE(CLK_GOUT_CMU_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus",
1292 GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0",
1294 GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1",
1296 GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2",
1298 GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3",
1300 GATE(CLK_GOUT_CMU_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4",
1302 GATE(CLK_GOUT_CMU_CIS_CLK5, "gout_cmu_cis_clk5", "mout_cmu_cis_clk5",
1304 GATE(CLK_GOUT_CMU_CIS_CLK6, "gout_cmu_cis_clk6", "mout_cmu_cis_clk6",
1306 GATE(CLK_GOUT_CMU_CIS_CLK7, "gout_cmu_cis_clk7", "mout_cmu_cis_clk7",
1308 GATE(CLK_GOUT_CMU_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_cmu_boost",
1310 GATE(CLK_GOUT_CMU_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",
1312 GATE(CLK_GOUT_CMU_CPUCL0_DBG, "gout_cmu_cpucl0_dbg",
1315 GATE(CLK_GOUT_CMU_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch",
1318 GATE(CLK_GOUT_CMU_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch",
1321 GATE(CLK_GOUT_CMU_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch",
1324 GATE(CLK_GOUT_CMU_CSIS_BUS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
1326 GATE(CLK_GOUT_CMU_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus",
1328 GATE(CLK_GOUT_CMU_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus",
1330 GATE(CLK_GOUT_CMU_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus",
1332 GATE(CLK_GOUT_CMU_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus",
1334 GATE(CLK_GOUT_CMU_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
1336 GATE(CLK_GOUT_CMU_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",
1338 GATE(CLK_GOUT_CMU_G3AA_G3AA, "gout_cmu_g3aa_g3aa", "mout_cmu_g3aa_g3aa",
1340 GATE(CLK_GOUT_CMU_G3D_BUSD, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd",
1342 GATE(CLK_GOUT_CMU_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb",
1344 GATE(CLK_GOUT_CMU_G3D_SWITCH, "gout_cmu_g3d_switch",
1347 GATE(CLK_GOUT_CMU_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0",
1349 GATE(CLK_GOUT_CMU_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1",
1351 GATE(CLK_GOUT_CMU_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc",
1353 GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
1355 GATE(CLK_GOUT_CMU_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus",
1357 GATE(CLK_GOUT_CMU_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc",
1360 GATE(CLK_GOUT_CMU_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd",
1363 GATE(CLK_GOUT_CMU_HSI0_USBDPDBG, "gout_cmu_hsi0_usbdpdbg",
1366 GATE(CLK_GOUT_CMU_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus",
1368 GATE(CLK_GOUT_CMU_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie",
1370 GATE(CLK_GOUT_CMU_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus",
1372 GATE(CLK_GOUT_CMU_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card",
1375 GATE(CLK_GOUT_CMU_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie",
1377 GATE(CLK_GOUT_CMU_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd",
1380 GATE(CLK_GOUT_CMU_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
1382 GATE(CLK_GOUT_CMU_ITP_BUS, "gout_cmu_itp_bus", "mout_cmu_itp_bus",
1384 GATE(CLK_GOUT_CMU_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc",
1386 GATE(CLK_GOUT_CMU_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc",
1388 GATE(CLK_GOUT_CMU_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc",
1390 GATE(CLK_GOUT_CMU_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp",
1392 GATE(CLK_GOUT_CMU_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus",
1394 GATE(CLK_GOUT_CMU_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss",
1396 GATE(CLK_GOUT_CMU_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",
1398 GATE(CLK_GOUT_CMU_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra",
1400 GATE(CLK_GOUT_CMU_PERIC0_BUS, "gout_cmu_peric0_bus",
1403 GATE(CLK_GOUT_CMU_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip",
1405 GATE(CLK_GOUT_CMU_PERIC1_BUS, "gout_cmu_peric1_bus",
1408 GATE(CLK_GOUT_CMU_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip",
1410 GATE(CLK_GOUT_CMU_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus",
1412 GATE(CLK_GOUT_CMU_TOP_CMUREF, "gout_cmu_top_cmuref",
1415 GATE(CLK_GOUT_CMU_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus",
1417 GATE(CLK_GOUT_CMU_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu",
1419 GATE(CLK_GOUT_CMU_TPU_TPUCTL, "gout_cmu_tpu_tpuctl",
1422 GATE(CLK_GOUT_CMU_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart",
1680 GATE(CLK_GOUT_APM_APM_CMU_APM_PCLK,
1683 GATE(CLK_GOUT_BUS0_BOOST_OPTION1, "gout_bus0_boost_option1",
1685 GATE(CLK_GOUT_CMU_BOOST_OPTION1, "gout_cmu_boost_option1",
1687 GATE(CLK_GOUT_CORE_BOOST_OPTION1, "gout_core_boost_option1",
1689 GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func",
1691 GATE(CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK,
1695 GATE(CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK,
1699 GATE(CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK,
1703 GATE(CLK_GOUT_APM_APBIF_RTC_PCLK,
1706 GATE(CLK_GOUT_APM_APBIF_TRTC_PCLK,
1709 GATE(CLK_GOUT_APM_APM_USI0_UART_IPCLK,
1713 GATE(CLK_GOUT_APM_APM_USI0_UART_PCLK,
1717 GATE(CLK_GOUT_APM_APM_USI0_USI_IPCLK,
1721 GATE(CLK_GOUT_APM_APM_USI0_USI_PCLK,
1725 GATE(CLK_GOUT_APM_APM_USI1_UART_IPCLK,
1729 GATE(CLK_GOUT_APM_APM_USI1_UART_PCLK,
1733 GATE(CLK_GOUT_APM_D_TZPC_APM_PCLK,
1736 GATE(CLK_GOUT_APM_GPC_APM_PCLK,
1739 GATE(CLK_GOUT_APM_GREBEINTEGRATION_HCLK,
1743 GATE(CLK_GOUT_APM_INTMEM_ACLK,
1746 GATE(CLK_GOUT_APM_INTMEM_PCLK,
1749 GATE(CLK_GOUT_APM_LHM_AXI_G_SWD_I_CLK,
1753 GATE(CLK_GOUT_APM_LHM_AXI_P_AOCAPM_I_CLK,
1757 GATE(CLK_GOUT_APM_LHM_AXI_P_APM_I_CLK,
1761 GATE(CLK_GOUT_APM_LHS_AXI_D_APM_I_CLK,
1765 GATE(CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK,
1769 GATE(CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_I_CLK,
1774 GATE(CLK_GOUT_APM_MAILBOX_APM_AOC_PCLK,
1778 GATE(CLK_GOUT_APM_MAILBOX_APM_AP_PCLK,
1782 GATE(CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK,
1786 GATE(CLK_GOUT_APM_MAILBOX_APM_SWD_PCLK,
1790 GATE(CLK_GOUT_APM_MAILBOX_APM_TPU_PCLK,
1794 GATE(CLK_GOUT_APM_MAILBOX_AP_AOC_PCLK,
1798 GATE(CLK_GOUT_APM_MAILBOX_AP_DBGCORE_PCLK,
1802 GATE(CLK_GOUT_APM_PMU_INTR_GEN_PCLK,
1806 GATE(CLK_GOUT_APM_ROM_CRC32_HOST_ACLK,
1810 GATE(CLK_GOUT_APM_ROM_CRC32_HOST_PCLK,
1814 GATE(CLK_GOUT_APM_CLK_APM_BUS_CLK,
1818 GATE(CLK_GOUT_APM_CLK_APM_USI0_UART_CLK,
1823 GATE(CLK_GOUT_APM_CLK_APM_USI0_USI_CLK,
1828 GATE(CLK_GOUT_APM_CLK_APM_USI1_UART_CLK,
1833 GATE(CLK_GOUT_APM_SPEEDY_APM_PCLK,
1836 GATE(CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK,
1840 GATE(CLK_GOUT_APM_SSMT_D_APM_ACLK,
1843 GATE(CLK_GOUT_APM_SSMT_D_APM_PCLK,
1846 GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_ACLK,
1850 GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_PCLK,
1854 GATE(CLK_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK,
1859 GATE(CLK_GOUT_APM_SYSMMU_D_APM_CLK_S2,
1863 GATE(CLK_GOUT_APM_SYSREG_APM_PCLK,
1866 GATE(CLK_GOUT_APM_UASC_APM_ACLK,
1869 GATE(CLK_GOUT_APM_UASC_APM_PCLK,
1872 GATE(CLK_GOUT_APM_UASC_DBGCORE_ACLK,
1876 GATE(CLK_GOUT_APM_UASC_DBGCORE_PCLK,
1880 GATE(CLK_GOUT_APM_UASC_G_SWD_ACLK,
1883 GATE(CLK_GOUT_APM_UASC_G_SWD_PCLK,
1886 GATE(CLK_GOUT_APM_UASC_P_AOCAPM_ACLK,
1890 GATE(CLK_GOUT_APM_UASC_P_AOCAPM_PCLK,
1893 GATE(CLK_GOUT_APM_UASC_P_APM_ACLK,
1896 GATE(CLK_GOUT_APM_UASC_P_APM_PCLK,
1899 GATE(CLK_GOUT_APM_WDT_APM_PCLK,
1902 GATE(CLK_GOUT_APM_XIU_DP_APM_ACLK,
2202 GATE(CLK_GOUT_MISC_MISC_CMU_MISC_PCLK,
2206 GATE(CLK_GOUT_MISC_OTP_CON_BIRA_I_OSCCLK,
2210 GATE(CLK_GOUT_MISC_OTP_CON_BISR_I_OSCCLK,
2214 GATE(CLK_GOUT_MISC_OTP_CON_TOP_I_OSCCLK,
2218 GATE(CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK,
2222 GATE(CLK_GOUT_MISC_ADM_AHB_SSS_HCLKM,
2226 GATE(CLK_GOUT_MISC_AD_APB_DIT_PCLKM,
2230 GATE(CLK_GOUT_MISC_D_TZPC_MISC_PCLK,
2234 GATE(CLK_GOUT_MISC_GIC_GICCLK,
2238 GATE(CLK_GOUT_MISC_GPC_MISC_PCLK,
2242 GATE(CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_I_CLK,
2246 GATE(CLK_GOUT_MISC_LHM_AXI_D_SSS_I_CLK,
2250 GATE(CLK_GOUT_MISC_LHM_AXI_P_GIC_I_CLK,
2254 GATE(CLK_GOUT_MISC_LHM_AXI_P_MISC_I_CLK,
2258 GATE(CLK_GOUT_MISC_LHS_ACEL_D_MISC_I_CLK,
2262 GATE(CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_I_CLK,
2266 GATE(CLK_GOUT_MISC_LHS_AXI_D_SSS_I_CLK,
2270 GATE(CLK_GOUT_MISC_MCT_PCLK, "gout_misc_mct_pclk",
2274 GATE(CLK_GOUT_MISC_OTP_CON_BIRA_PCLK,
2278 GATE(CLK_GOUT_MISC_OTP_CON_BISR_PCLK,
2282 GATE(CLK_GOUT_MISC_OTP_CON_TOP_PCLK,
2286 GATE(CLK_GOUT_MISC_PDMA_ACLK, "gout_misc_pdma_aclk",
2290 GATE(CLK_GOUT_MISC_PPMU_MISC_ACLK,
2294 GATE(CLK_GOUT_MISC_PPMU_MISC_PCLK,
2298 GATE(CLK_GOUT_MISC_PUF_I_CLK,
2302 GATE(CLK_GOUT_MISC_QE_DIT_ACLK,
2306 GATE(CLK_GOUT_MISC_QE_DIT_PCLK,
2310 GATE(CLK_GOUT_MISC_QE_PDMA_ACLK,
2314 GATE(CLK_GOUT_MISC_QE_PDMA_PCLK,
2318 GATE(CLK_GOUT_MISC_QE_PPMU_DMA_ACLK,
2322 GATE(CLK_GOUT_MISC_QE_PPMU_DMA_PCLK,
2326 GATE(CLK_GOUT_MISC_QE_RTIC_ACLK,
2330 GATE(CLK_GOUT_MISC_QE_RTIC_PCLK,
2334 GATE(CLK_GOUT_MISC_QE_SPDMA_ACLK,
2338 GATE(CLK_GOUT_MISC_QE_SPDMA_PCLK,
2342 GATE(CLK_GOUT_MISC_QE_SSS_ACLK,
2346 GATE(CLK_GOUT_MISC_QE_SSS_PCLK,
2350 GATE(CLK_GOUT_MISC_CLK_MISC_BUSD_CLK,
2354 GATE(CLK_GOUT_MISC_CLK_MISC_BUSP_CLK,
2358 GATE(CLK_GOUT_MISC_CLK_MISC_GIC_CLK,
2362 GATE(CLK_GOUT_MISC_CLK_MISC_SSS_CLK,
2366 GATE(CLK_GOUT_MISC_RTIC_I_ACLK,
2370 GATE(CLK_GOUT_MISC_RTIC_I_PCLK, "gout_misc_rtic_i_pclk",
2374 GATE(CLK_GOUT_MISC_SPDMA_ACLK,
2378 GATE(CLK_GOUT_MISC_SSMT_DIT_ACLK,
2382 GATE(CLK_GOUT_MISC_SSMT_DIT_PCLK,
2386 GATE(CLK_GOUT_MISC_SSMT_PDMA_ACLK,
2390 GATE(CLK_GOUT_MISC_SSMT_PDMA_PCLK,
2394 GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_ACLK,
2398 GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_PCLK,
2402 GATE(CLK_GOUT_MISC_SSMT_RTIC_ACLK,
2406 GATE(CLK_GOUT_MISC_SSMT_RTIC_PCLK,
2410 GATE(CLK_GOUT_MISC_SSMT_SPDMA_ACLK,
2414 GATE(CLK_GOUT_MISC_SSMT_SPDMA_PCLK,
2418 GATE(CLK_GOUT_MISC_SSMT_SSS_ACLK,
2422 GATE(CLK_GOUT_MISC_SSMT_SSS_PCLK,
2426 GATE(CLK_GOUT_MISC_SSS_I_ACLK,
2430 GATE(CLK_GOUT_MISC_SSS_I_PCLK,
2434 GATE(CLK_GOUT_MISC_SYSMMU_MISC_CLK_S2,
2438 GATE(CLK_GOUT_MISC_SYSMMU_SSS_CLK_S1,
2442 GATE(CLK_GOUT_MISC_SYSREG_MISC_PCLK,
2446 GATE(CLK_GOUT_MISC_TMU_SUB_PCLK,
2450 GATE(CLK_GOUT_MISC_TMU_TOP_PCLK,
2454 GATE(CLK_GOUT_MISC_WDT_CLUSTER0_PCLK,
2458 GATE(CLK_GOUT_MISC_WDT_CLUSTER1_PCLK,
2462 GATE(CLK_GOUT_MISC_XIU_D_MISC_ACLK,