Lines Matching +full:0 +full:x3060
26 /* Register Offset definitions for CMU_TOP (0x1e080000) */
28 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
29 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
30 #define PLL_LOCKTIME_PLL_SHARED2 0x0008
31 #define PLL_LOCKTIME_PLL_SHARED3 0x000c
32 #define PLL_LOCKTIME_PLL_SPARE 0x0010
33 #define PLL_CON0_PLL_SHARED0 0x0100
34 #define PLL_CON1_PLL_SHARED0 0x0104
35 #define PLL_CON2_PLL_SHARED0 0x0108
36 #define PLL_CON3_PLL_SHARED0 0x010c
37 #define PLL_CON4_PLL_SHARED0 0x0110
38 #define PLL_CON0_PLL_SHARED1 0x0140
39 #define PLL_CON1_PLL_SHARED1 0x0144
40 #define PLL_CON2_PLL_SHARED1 0x0148
41 #define PLL_CON3_PLL_SHARED1 0x014c
42 #define PLL_CON4_PLL_SHARED1 0x0150
43 #define PLL_CON0_PLL_SHARED2 0x0180
44 #define PLL_CON1_PLL_SHARED2 0x0184
45 #define PLL_CON2_PLL_SHARED2 0x0188
46 #define PLL_CON3_PLL_SHARED2 0x018c
47 #define PLL_CON4_PLL_SHARED2 0x0190
48 #define PLL_CON0_PLL_SHARED3 0x01c0
49 #define PLL_CON1_PLL_SHARED3 0x01c4
50 #define PLL_CON2_PLL_SHARED3 0x01c8
51 #define PLL_CON3_PLL_SHARED3 0x01cc
52 #define PLL_CON4_PLL_SHARED3 0x01d0
53 #define PLL_CON0_PLL_SPARE 0x0200
54 #define PLL_CON1_PLL_SPARE 0x0204
55 #define PLL_CON2_PLL_SPARE 0x0208
56 #define PLL_CON3_PLL_SPARE 0x020c
57 #define PLL_CON4_PLL_SPARE 0x0210
58 #define CMU_CMU_TOP_CONTROLLER_OPTION 0x0800
59 #define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0 0x0810
60 #define CMU_HCHGEN_CLKMUX_CMU_BOOST 0x0840
61 #define CMU_HCHGEN_CLKMUX_TOP_BOOST 0x0844
62 #define CMU_HCHGEN_CLKMUX 0x0850
63 #define POWER_FAIL_DETECT_PLL 0x0864
64 #define EARLY_WAKEUP_FORCED_0_ENABLE 0x0870
65 #define EARLY_WAKEUP_FORCED_1_ENABLE 0x0874
66 #define EARLY_WAKEUP_APM_CTRL 0x0878
67 #define EARLY_WAKEUP_CLUSTER0_CTRL 0x087c
68 #define EARLY_WAKEUP_DPU_CTRL 0x0880
69 #define EARLY_WAKEUP_CSIS_CTRL 0x0884
70 #define EARLY_WAKEUP_APM_DEST 0x0890
71 #define EARLY_WAKEUP_CLUSTER0_DEST 0x0894
72 #define EARLY_WAKEUP_DPU_DEST 0x0898
73 #define EARLY_WAKEUP_CSIS_DEST 0x089c
74 #define EARLY_WAKEUP_SW_TRIG_APM 0x08c0
75 #define EARLY_WAKEUP_SW_TRIG_APM_SET 0x08c4
76 #define EARLY_WAKEUP_SW_TRIG_APM_CLEAR 0x08c8
77 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0 0x08d0
78 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET 0x08d4
79 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR 0x08d8
80 #define EARLY_WAKEUP_SW_TRIG_DPU 0x08e0
81 #define EARLY_WAKEUP_SW_TRIG_DPU_SET 0x08e4
82 #define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR 0x08e8
83 #define EARLY_WAKEUP_SW_TRIG_CSIS 0x08f0
84 #define EARLY_WAKEUP_SW_TRIG_CSIS_SET 0x08f4
85 #define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR 0x08f8
86 #define CLK_CON_MUX_MUX_CLKCMU_BO_BUS 0x1000
87 #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x1004
88 #define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1008
89 #define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS 0x100c
90 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1010
91 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1014
92 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1018
93 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x101c
94 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1020
95 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x1024
96 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 0x1028
97 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 0x102c
98 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030
99 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1 0x1034
100 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1038
101 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x103c
102 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1040
103 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1044
104 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048
105 #define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c
106 #define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS 0x1050
107 #define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x1054
108 #define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS 0x1058
109 #define CLK_CON_MUX_MUX_CLKCMU_EH_BUS 0x105c
110 #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1060
111 #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1064
112 #define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA 0x1068
113 #define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD 0x106c
114 #define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB 0x1070
115 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1074
116 #define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0 0x1078
117 #define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1 0x107c
118 #define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC 0x1080
119 #define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1084
120 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1088
121 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x108c
122 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1090
123 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG 0x1094
124 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1098
125 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x109c
126 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x10a0
127 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD 0x10a4
128 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a8
129 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x10ac
130 #define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10b0
131 #define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10b4
132 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC 0x10b8
133 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC 0x10bc
134 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10c0
135 #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c4
136 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c8
137 #define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS 0x10cc
138 #define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS 0x10d0
139 #define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS 0x10d4
140 #define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA 0x10d8
141 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10dc
142 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10e0
143 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10e4
144 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10e8
145 #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10ec
146 #define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1 0x10f0
147 #define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF 0x10f4
148 #define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS 0x10f8
149 #define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU 0x10fc
150 #define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL 0x1100
151 #define CLK_CON_MUX_MUX_CLKCMU_TPU_UART 0x1104
152 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x1108
153 #define CLK_CON_DIV_CLKCMU_BO_BUS 0x1800
154 #define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1804
155 #define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x1808
156 #define CLK_CON_DIV_CLKCMU_BUS2_BUS 0x180c
157 #define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1810
158 #define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1814
159 #define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1818
160 #define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x181c
161 #define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1820
162 #define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1824
163 #define CLK_CON_DIV_CLKCMU_CIS_CLK6 0x1828
164 #define CLK_CON_DIV_CLKCMU_CIS_CLK7 0x182c
165 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830
166 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1834
167 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838
168 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
169 #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1840
170 #define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1844
171 #define CLK_CON_DIV_CLKCMU_DISP_BUS 0x1848
172 #define CLK_CON_DIV_CLKCMU_DNS_BUS 0x184c
173 #define CLK_CON_DIV_CLKCMU_DPU_BUS 0x1850
174 #define CLK_CON_DIV_CLKCMU_EH_BUS 0x1854
175 #define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1858
176 #define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x185c
177 #define CLK_CON_DIV_CLKCMU_G3AA_G3AA 0x1860
178 #define CLK_CON_DIV_CLKCMU_G3D_BUSD 0x1864
179 #define CLK_CON_DIV_CLKCMU_G3D_GLB 0x1868
180 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x186c
181 #define CLK_CON_DIV_CLKCMU_GDC_GDC0 0x1870
182 #define CLK_CON_DIV_CLKCMU_GDC_GDC1 0x1874
183 #define CLK_CON_DIV_CLKCMU_GDC_SCSC 0x1878
184 #define CLK_CON_DIV_CLKCMU_HPM 0x187c
185 #define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1880
186 #define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1884
187 #define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1888
188 #define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG 0x188c
189 #define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1890
190 #define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1894
191 #define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1898
192 #define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD 0x189c
193 #define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x18a0
194 #define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x18a4
195 #define CLK_CON_DIV_CLKCMU_IPP_BUS 0x18a8
196 #define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18ac
197 #define CLK_CON_DIV_CLKCMU_MCSC_ITSC 0x18b0
198 #define CLK_CON_DIV_CLKCMU_MCSC_MCSC 0x18b4
199 #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18b8
200 #define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18bc
201 #define CLK_CON_DIV_CLKCMU_MISC_BUS 0x18c0
202 #define CLK_CON_DIV_CLKCMU_MISC_SSS 0x18c4
203 #define CLK_CON_DIV_CLKCMU_OTP 0x18c8
204 #define CLK_CON_DIV_CLKCMU_PDP_BUS 0x18cc
205 #define CLK_CON_DIV_CLKCMU_PDP_VRA 0x18d0
206 #define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18d4
207 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18d8
208 #define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18dc
209 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18e0
210 #define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18e4
211 #define CLK_CON_DIV_CLKCMU_TPU_BUS 0x18e8
212 #define CLK_CON_DIV_CLKCMU_TPU_TPU 0x18ec
213 #define CLK_CON_DIV_CLKCMU_TPU_TPUCTL 0x18f0
214 #define CLK_CON_DIV_CLKCMU_TPU_UART 0x18f4
215 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18f8
216 #define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18fc
217 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x1900
218 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1904
219 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1908
220 #define CLK_CON_DIV_PLL_SHARED0_DIV5 0x190c
221 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1910
222 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1914
223 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1918
224 #define CLK_CON_DIV_PLL_SHARED2_DIV2 0x191c
225 #define CLK_CON_DIV_PLL_SHARED3_DIV2 0x1920
226 #define CLK_CON_GAT_CLKCMU_BUS0_BOOST 0x2000
227 #define CLK_CON_GAT_CLKCMU_BUS1_BOOST 0x2004
228 #define CLK_CON_GAT_CLKCMU_BUS2_BOOST 0x2008
229 #define CLK_CON_GAT_CLKCMU_CORE_BOOST 0x200c
230 #define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST 0x2010
231 #define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST 0x2014
232 #define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST 0x2018
233 #define CLK_CON_GAT_CLKCMU_MIF_BOOST 0x201c
234 #define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2020
235 #define CLK_CON_GAT_GATE_CLKCMU_BO_BUS 0x2024
236 #define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2028
237 #define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x202c
238 #define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS 0x2030
239 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2034
240 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2038
241 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x203c
242 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2040
243 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x2044
244 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2048
245 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 0x204c
246 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 0x2050
247 #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2054
248 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2058
249 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x205c
250 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2060
251 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2064
252 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2068
253 #define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x206c
254 #define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS 0x2070
255 #define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x2074
256 #define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2078
257 #define CLK_CON_GAT_GATE_CLKCMU_EH_BUS 0x207c
258 #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2080
259 #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2084
260 #define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA 0x2088
261 #define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD 0x208c
262 #define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB 0x2090
263 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2094
264 #define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0 0x2098
265 #define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1 0x209c
266 #define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC 0x20a0
267 #define CLK_CON_GAT_GATE_CLKCMU_HPM 0x20a4
268 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x20a8
269 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x20ac
270 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x20b0
271 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG 0x20b4
272 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x20b8
273 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x20bc
274 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20c0
275 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD 0x20c4
276 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20c8
277 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD 0x20cc
278 #define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20d0
279 #define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20d4
280 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC 0x20d8
281 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC 0x20dc
282 #define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20e0
283 #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20e4
284 #define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS 0x20e8
285 #define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS 0x20ec
286 #define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS 0x20f0
287 #define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA 0x20f4
288 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20f8
289 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20fc
290 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x2100
291 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x2104
292 #define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x2108
293 #define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF 0x210c
294 #define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS 0x2110
295 #define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU 0x2114
296 #define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL 0x2118
297 #define CLK_CON_GAT_GATE_CLKCMU_TPU_UART 0x211c
298 #define DMYQCH_CON_CMU_TOP_CMUREF_QCH 0x3000
299 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0 0x3004
300 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1 0x3008
301 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2 0x300c
302 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3 0x3010
303 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4 0x3014
304 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5 0x3018
305 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6 0x301c
306 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7 0x3020
307 #define DMYQCH_CON_OTP_QCH 0x3024
308 #define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP 0x3c00
309 #define QUEUE_ENTRY0_BLK_CMU_CMU_TOP 0x3c10
310 #define QUEUE_ENTRY1_BLK_CMU_CMU_TOP 0x3c14
311 #define QUEUE_ENTRY2_BLK_CMU_CMU_TOP 0x3c18
312 #define QUEUE_ENTRY3_BLK_CMU_CMU_TOP 0x3c1c
313 #define QUEUE_ENTRY4_BLK_CMU_CMU_TOP 0x3c20
314 #define QUEUE_ENTRY5_BLK_CMU_CMU_TOP 0x3c24
315 #define QUEUE_ENTRY6_BLK_CMU_CMU_TOP 0x3c28
316 #define QUEUE_ENTRY7_BLK_CMU_CMU_TOP 0x3c2c
317 #define MIFMIRROR_QUEUE_CTRL_REG 0x3e00
318 #define MIFMIRROR_QUEUE_ENTRY0 0x3e10
319 #define MIFMIRROR_QUEUE_ENTRY1 0x3e14
320 #define MIFMIRROR_QUEUE_ENTRY2 0x3e18
321 #define MIFMIRROR_QUEUE_ENTRY3 0x3e1c
322 #define MIFMIRROR_QUEUE_ENTRY4 0x3e20
323 #define MIFMIRROR_QUEUE_ENTRY5 0x3e24
324 #define MIFMIRROR_QUEUE_ENTRY6 0x3e28
325 #define MIFMIRROR_QUEUE_ENTRY7 0x3e2c
326 #define MIFMIRROR_QUEUE_BUSY 0x3e30
327 #define GENERALIO_ACD_CHANNEL_0 0x3f00
328 #define GENERALIO_ACD_CHANNEL_1 0x3f04
329 #define GENERALIO_ACD_CHANNEL_2 0x3f08
330 #define GENERALIO_ACD_CHANNEL_3 0x3f0c
331 #define GENERALIO_ACD_MASK 0x3f14
966 CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 3),
968 CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 3),
970 CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 3),
972 CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 3),
974 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 3),
976 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 3),
978 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 3),
980 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 3),
982 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0, 3),
984 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0, 3),
986 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 0, 3),
988 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 0, 3),
990 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
993 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, 0, 1),
995 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),
997 mout_cmu_cpucl0_dbg_p, CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3),
1000 0, 3),
1003 0, 3),
1006 0, 3),
1008 CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 3),
1010 CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 3),
1012 CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 3),
1014 CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 3),
1016 CLK_CON_MUX_MUX_CLKCMU_EH_BUS, 0, 3),
1018 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3),
1020 CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 3),
1022 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 3),
1024 CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 3),
1026 CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 3),
1028 mout_cmu_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 3),
1030 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 3),
1032 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 3),
1034 CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 3),
1036 CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
1038 CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 3),
1040 mout_cmu_hsi0_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2),
1043 0, 1),
1046 0, 1),
1048 CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3),
1050 CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 1),
1052 CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 3),
1055 0, 2),
1057 CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 1),
1060 0, 2),
1062 CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 3),
1064 CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 3),
1066 CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 3),
1068 CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 3),
1070 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 3),
1072 CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
1074 mout_cmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
1076 CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2),
1078 CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2),
1080 CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 3),
1082 CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 3),
1084 mout_cmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
1086 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
1088 mout_cmu_peric1_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 2),
1090 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 2),
1092 CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3),
1095 CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, 0, 1),
1097 mout_cmu_top_cmuref_p, CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, 0, 2),
1099 CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 3),
1101 CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 3),
1103 mout_cmu_tpu_tpuctl_p, CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 3),
1105 CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2),
1107 CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
1112 CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4),
1114 CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4),
1116 CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),
1118 CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4),
1120 CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5),
1122 CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5),
1124 CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5),
1126 CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5),
1128 CLK_CON_DIV_CLKCMU_CIS_CLK4, 0, 5),
1130 CLK_CON_DIV_CLKCMU_CIS_CLK5, 0, 5),
1132 CLK_CON_DIV_CLKCMU_CIS_CLK6, 0, 5),
1134 CLK_CON_DIV_CLKCMU_CIS_CLK7, 0, 5),
1136 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
1138 "gout_cmu_cpucl0_dbg", CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),
1140 "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
1142 "gout_cmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
1144 "gout_cmu_cpucl2_switch", CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
1146 CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4),
1148 CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4),
1150 CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4),
1152 CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4),
1154 CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4),
1156 CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
1158 CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
1160 CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4),
1162 CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4),
1164 CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4),
1166 "gout_cmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
1168 CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4),
1170 CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4),
1172 CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4),
1174 CLK_CON_DIV_CLKCMU_HPM, 0, 2),
1176 CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4),
1178 "gout_cmu_hsi0_dpgtc", CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4),
1180 "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5),
1182 CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4),
1184 CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3),
1186 CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
1188 "gout_cmu_hsi2_mmc_card", CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9),
1190 CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3),
1192 "gout_cmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4),
1194 CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
1196 CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4),
1198 CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4),
1200 CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4),
1202 CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
1204 CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
1206 CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4),
1208 CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4),
1210 CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4),
1212 CLK_CON_DIV_CLKCMU_PDP_VRA, 0, 4),
1214 "gout_cmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
1216 CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
1218 "gout_cmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
1220 CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
1222 CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
1224 CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4),
1226 CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4),
1228 "gout_cmu_tpu_tpuctl", CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4),
1230 CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4),
1232 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
1234 CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2),
1236 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
1238 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
1240 "dout_cmu_shared0_div2", CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
1242 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
1244 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
1246 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
1248 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
1250 "mout_pll_shared2", CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
1252 "mout_pll_shared3", CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1),
1257 "gout_cmu_hsi0_usbdpdbg", 1, 4, 0),
1258 FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0),
1263 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0),
1265 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS1_BOOST, 21, 0, 0),
1267 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS2_BOOST, 21, 0, 0),
1269 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CORE_BOOST, 21, 0, 0),
1272 21, 0, 0),
1275 21, 0, 0),
1278 21, 0, 0),
1281 21, 0, 0),
1283 "mout_cmu_mif_switch", CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0),
1285 CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0),
1287 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0),
1289 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0),
1291 CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0),
1293 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0),
1295 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0),
1297 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0),
1299 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0),
1301 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 21, 0, 0),
1303 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 21, 0, 0),
1305 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 21, 0, 0),
1307 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 21, 0, 0),
1309 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0),
1311 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
1314 21, 0, 0),
1317 21, 0, 0),
1320 21, 0, 0),
1323 21, 0, 0),
1325 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
1327 CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0),
1329 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0),
1331 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0),
1333 CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0),
1335 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
1337 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),
1339 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0),
1341 CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0),
1343 CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0),
1346 21, 0, 0),
1348 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0),
1350 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0),
1352 CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0),
1354 CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
1356 CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0),
1359 21, 0, 0),
1362 21, 0, 0),
1365 21, 0, 0),
1367 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0),
1369 CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0),
1371 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0),
1374 21, 0, 0),
1376 CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0),
1379 21, 0, 0),
1381 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
1383 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0),
1385 CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0),
1387 CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0),
1389 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
1391 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0),
1393 CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0),
1395 CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0),
1397 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
1399 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
1402 21, 0, 0),
1404 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0),
1407 21, 0, 0),
1409 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0),
1411 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0),
1414 21, 0, 0),
1416 CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0),
1418 CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0),
1421 21, 0, 0),
1423 CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0),
1453 /* Register Offset definitions for CMU_APM (0x17400000) */
1454 #define APM_CMU_APM_CONTROLLER_OPTION 0x0800
1455 #define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810
1456 #define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000
1457 #define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004
1458 #define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800
1459 #define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804
1460 #define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808
1461 #define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c
1462 #define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000
1463 #define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004
1464 #define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008
1465 #define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c
1466 #define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010
1467 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014
1468 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018
1469 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c
1470 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020
1471 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024
1472 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028
1473 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c
1474 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030
1475 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034
1476 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038
1477 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c
1478 #define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040
1479 #define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044
1480 #define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048
1481 #define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c
1482 #define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050
1483 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054
1484 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058
1485 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c
1486 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060
1487 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064
1488 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068
1489 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c
1490 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070
1491 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074
1492 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c
1493 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080
1494 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084
1495 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088
1496 #define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c
1497 #define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090
1498 #define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094
1499 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098
1500 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c
1501 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0
1502 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4
1503 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8
1504 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac
1505 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0
1506 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4
1507 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8
1508 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc
1509 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0
1510 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4
1511 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc
1512 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0
1513 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4
1514 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8
1515 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc
1516 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0
1517 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4
1518 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8
1519 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec
1520 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0
1521 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4
1522 #define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8
1523 #define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc
1524 #define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000
1525 #define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004
1526 #define PCH_CON_LHM_AXI_P_APM_PCH 0x3008
1527 #define PCH_CON_LHS_AXI_D_APM_PCH 0x300c
1528 #define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010
1529 #define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014
1530 #define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018
1531 #define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c
1532 #define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020
1533 #define QCH_CON_APBIF_RTC_QCH 0x3024
1534 #define QCH_CON_APBIF_TRTC_QCH 0x3028
1535 #define QCH_CON_APM_CMU_APM_QCH 0x302c
1536 #define QCH_CON_APM_USI0_UART_QCH 0x3030
1537 #define QCH_CON_APM_USI0_USI_QCH 0x3034
1538 #define QCH_CON_APM_USI1_UART_QCH 0x3038
1539 #define QCH_CON_D_TZPC_APM_QCH 0x303c
1540 #define QCH_CON_GPC_APM_QCH 0x3040
1541 #define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044
1542 #define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048
1543 #define QCH_CON_INTMEM_QCH 0x304c
1544 #define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050
1545 #define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054
1546 #define QCH_CON_LHM_AXI_P_APM_QCH 0x3058
1547 #define QCH_CON_LHS_AXI_D_APM_QCH 0x305c
1548 #define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060
1549 #define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064
1550 #define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068
1551 #define QCH_CON_MAILBOX_APM_AP_QCH 0x306c
1552 #define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070
1553 #define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078
1554 #define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c
1555 #define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080
1556 #define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084
1557 #define QCH_CON_PMU_INTR_GEN_QCH 0x3088
1558 #define QCH_CON_ROM_CRC32_HOST_QCH 0x308c
1559 #define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090
1560 #define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094
1561 #define QCH_CON_SPEEDY_APM_QCH 0x3098
1562 #define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c
1563 #define QCH_CON_SSMT_D_APM_QCH 0x30a0
1564 #define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4
1565 #define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8
1566 #define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac
1567 #define QCH_CON_SYSMMU_D_APM_QCH 0x30b0
1568 #define QCH_CON_SYSREG_APM_QCH 0x30b8
1569 #define QCH_CON_UASC_APM_QCH 0x30bc
1570 #define QCH_CON_UASC_DBGCORE_QCH 0x30c0
1571 #define QCH_CON_UASC_G_SWD_QCH 0x30c4
1572 #define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8
1573 #define QCH_CON_UASC_P_APM_QCH 0x30cc
1574 #define QCH_CON_WDT_APM_QCH 0x30d0
1575 #define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00
1656 FRATE(CLK_APM_PLL_DIV2_APM, "pll_alv_div2_apm", NULL, 0, 393216000),
1657 FRATE(CLK_APM_PLL_DIV4_APM, "pll_alv_div4_apm", NULL, 0, 196608000),
1658 FRATE(CLK_APM_PLL_DIV16_APM, "pll_alv_div16_apm", NULL, 0, 49152000),
1670 CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1),
1672 CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7),
1674 CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7),
1676 CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7),
1682 CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 21, 0, 0),
1684 "dout_apm_boost", CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, 21, 0, 0),
1686 "dout_apm_boost", CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, 21, 0, 0),
1688 "dout_apm_boost", CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, 21, 0, 0),
1690 CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0),
1694 21, 0, 0),
1698 21, 0, 0),
1702 21, 0, 0),
1705 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 21, 0, 0),
1708 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, 21, 0, 0),
1712 21, 0, 0),
1716 21, 0, 0),
1720 21, 0, 0),
1724 21, 0, 0),
1728 21, 0, 0),
1732 21, 0, 0),
1735 CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, 21, 0, 0),
1738 CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, 21, 0, 0),
1742 21, 0, 0),
1745 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 21, 0, 0),
1748 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 21, 0, 0),
1752 21, 0, 0),
1756 21, 0, 0),
1760 21, 0, 0),
1764 21, 0, 0),
1768 21, 0, 0),
1773 21, 0, 0),
1777 21, 0, 0),
1781 21, 0, 0),
1785 21, 0, 0),
1789 21, 0, 0),
1793 21, 0, 0),
1797 21, 0, 0),
1801 21, 0, 0),
1805 21, 0, 0),
1809 21, 0, 0),
1813 21, 0, 0),
1817 21, 0, 0),
1822 21, 0, 0),
1827 21, 0, 0),
1832 21, 0, 0),
1835 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, 21, 0, 0),
1839 21, 0, 0),
1842 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, 21, 0, 0),
1845 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, 21, 0, 0),
1849 21, 0, 0),
1853 21, 0, 0),
1858 21, 0, 0),
1862 21, 0, 0),
1865 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 21, 0, 0),
1868 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, 21, 0, 0),
1871 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, 21, 0, 0),
1875 21, 0, 0),
1879 21, 0, 0),
1882 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, 21, 0, 0),
1885 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0),
1889 21, 0, 0),
1892 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0),
1895 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 21, 0, 0),
1898 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, 0, 0),
1901 CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 21, 0, 0),
1904 CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, 0, 0),
1923 /* Register Offset definitions for CMU_MISC (0x10010000) */
1924 #define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER 0x0600
1925 #define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER 0x0604
1926 #define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER 0x0610
1927 #define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER 0x0614
1928 #define MISC_CMU_MISC_CONTROLLER_OPTION 0x0800
1929 #define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0 0x0810
1930 #define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000
1931 #define CLK_CON_DIV_DIV_CLK_MISC_BUSP 0x1800
1932 #define CLK_CON_DIV_DIV_CLK_MISC_GIC 0x1804
1933 #define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK 0x2000
1934 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2004
1935 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK 0x2008
1936 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x200c
1937 #define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK 0x2010
1938 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM 0x2014
1939 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM 0x2018
1940 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM 0x201c
1941 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A 0x2020
1942 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK 0x2024
1943 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK 0x2028
1944 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK 0x202c
1945 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK 0x2030
1946 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK 0x2034
1947 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK 0x2038
1948 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK 0x203c
1949 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK 0x2040
1950 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK 0x2044
1951 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK 0x2048
1952 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK 0x204c
1953 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2050
1954 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK 0x2054
1955 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2058
1956 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK 0x205c
1957 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK 0x2060
1958 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK 0x2064
1959 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK 0x2068
1960 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK 0x206c
1961 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK 0x2070
1962 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK 0x2074
1963 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK 0x2078
1964 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK 0x207c
1965 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK 0x2080
1966 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK 0x2084
1967 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK 0x2088
1968 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK 0x208c
1969 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK 0x2090
1970 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2094
1971 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK 0x2098
1972 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK 0x209c
1973 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK 0x20a0
1974 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK 0x20a4
1975 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK 0x20a8
1976 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK 0x20ac
1977 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK 0x20b0
1978 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK 0x20b4
1979 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK 0x20b8
1980 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK 0x20bc
1981 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK 0x20c0
1982 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK 0x20c4
1983 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK 0x20c8
1984 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK 0x20cc
1985 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK 0x20d0
1986 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK 0x20d4
1987 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK 0x20d8
1988 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK 0x20dc
1989 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK 0x20e0
1990 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK 0x20e4
1991 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK 0x20e8
1992 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK 0x20ec
1993 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK 0x20f0
1994 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2 0x20f4
1995 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1 0x20f8
1996 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK 0x20fc
1997 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK 0x2100
1998 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK 0x2104
1999 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2108
2000 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x210c
2001 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK 0x2110
2002 #define DMYQCH_CON_PPMU_DMA_QCH 0x3000
2003 #define DMYQCH_CON_PUF_QCH 0x3004
2004 #define PCH_CON_LHM_AXI_D_SSS_PCH 0x300c
2005 #define PCH_CON_LHM_AXI_P_GIC_PCH 0x3010
2006 #define PCH_CON_LHM_AXI_P_MISC_PCH 0x3014
2007 #define PCH_CON_LHS_ACEL_D_MISC_PCH 0x3018
2008 #define PCH_CON_LHS_AST_IRI_GICCPU_PCH 0x301c
2009 #define PCH_CON_LHS_AXI_D_SSS_PCH 0x3020
2010 #define QCH_CON_ADM_AHB_SSS_QCH 0x3024
2011 #define QCH_CON_DIT_QCH 0x3028
2012 #define QCH_CON_GIC_QCH 0x3030
2013 #define QCH_CON_LHM_AST_ICC_CPUGIC_QCH 0x3038
2014 #define QCH_CON_LHM_AXI_D_SSS_QCH 0x303c
2015 #define QCH_CON_LHM_AXI_P_GIC_QCH 0x3040
2016 #define QCH_CON_LHM_AXI_P_MISC_QCH 0x3044
2017 #define QCH_CON_LHS_ACEL_D_MISC_QCH 0x3048
2018 #define QCH_CON_LHS_AST_IRI_GICCPU_QCH 0x304c
2019 #define QCH_CON_LHS_AXI_D_SSS_QCH 0x3050
2020 #define QCH_CON_MCT_QCH 0x3054
2021 #define QCH_CON_MISC_CMU_MISC_QCH 0x3058
2022 #define QCH_CON_OTP_CON_BIRA_QCH 0x305c
2023 #define QCH_CON_OTP_CON_BISR_QCH 0x3060
2024 #define QCH_CON_OTP_CON_TOP_QCH 0x3064
2025 #define QCH_CON_PDMA_QCH 0x3068
2026 #define QCH_CON_PPMU_MISC_QCH 0x306c
2027 #define QCH_CON_QE_DIT_QCH 0x3070
2028 #define QCH_CON_QE_PDMA_QCH 0x3074
2029 #define QCH_CON_QE_PPMU_DMA_QCH 0x3078
2030 #define QCH_CON_QE_RTIC_QCH 0x307c
2031 #define QCH_CON_QE_SPDMA_QCH 0x3080
2032 #define QCH_CON_QE_SSS_QCH 0x3084
2033 #define QCH_CON_RTIC_QCH 0x3088
2034 #define QCH_CON_SPDMA_QCH 0x308c
2035 #define QCH_CON_SSMT_DIT_QCH 0x3090
2036 #define QCH_CON_SSMT_PDMA_QCH 0x3094
2037 #define QCH_CON_SSMT_PPMU_DMA_QCH 0x3098
2038 #define QCH_CON_SSMT_RTIC_QCH 0x309c
2039 #define QCH_CON_SSMT_SPDMA_QCH 0x30a0
2040 #define QCH_CON_SSMT_SSS_QCH 0x30a4
2041 #define QCH_CON_SSS_QCH 0x30a8
2042 #define QCH_CON_SYSMMU_MISC_QCH 0x30ac
2043 #define QCH_CON_SYSMMU_SSS_QCH 0x30b0
2044 #define QCH_CON_SYSREG_MISC_QCH 0x30b4
2045 #define QCH_CON_TMU_SUB_QCH 0x30b8
2046 #define QCH_CON_TMU_TOP_QCH 0x30bc
2047 #define QCH_CON_WDT_CLUSTER0_QCH 0x30c0
2048 #define QCH_CON_WDT_CLUSTER1_QCH 0x30c4
2049 #define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC 0x3c00
2191 CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 0),
2196 CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3),
2198 CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3),
2205 21, 0, 0),
2209 21, 0, 0),
2213 21, 0, 0),
2217 21, 0, 0),
2221 21, 0, 0),
2225 21, 0, 0),
2229 21, 0, 0),
2233 21, 0, 0),
2237 21, 0, 0),
2241 21, 0, 0),
2245 21, 0, 0),
2249 21, 0, 0),
2253 21, 0, 0),
2257 21, 0, 0),
2261 21, 0, 0),
2265 21, 0, 0),
2269 21, 0, 0),
2273 21, 0, 0),
2277 21, 0, 0),
2281 21, 0, 0),
2285 21, 0, 0),
2289 21, 0, 0),
2293 21, 0, 0),
2297 21, 0, 0),
2301 21, 0, 0),
2305 21, 0, 0),
2309 21, 0, 0),
2313 21, 0, 0),
2317 21, 0, 0),
2321 21, 0, 0),
2325 21, 0, 0),
2329 21, 0, 0),
2333 21, 0, 0),
2337 21, 0, 0),
2341 21, 0, 0),
2345 21, 0, 0),
2349 21, 0, 0),
2353 21, 0, 0),
2357 21, 0, 0),
2361 21, 0, 0),
2365 21, 0, 0),
2369 21, 0, 0),
2373 21, 0, 0),
2377 21, 0, 0),
2381 21, 0, 0),
2385 21, 0, 0),
2389 21, 0, 0),
2393 21, 0, 0),
2397 21, 0, 0),
2401 21, 0, 0),
2405 21, 0, 0),
2409 21, 0, 0),
2413 21, 0, 0),
2417 21, 0, 0),
2421 21, 0, 0),
2425 21, 0, 0),
2429 21, 0, 0),
2433 21, 0, 0),
2437 21, 0, 0),
2441 21, 0, 0),
2445 21, 0, 0),
2449 21, 0, 0),
2453 21, 0, 0),
2457 21, 0, 0),
2461 21, 0, 0),
2465 21, 0, 0),
2491 return 0; in gs101_cmu_probe()