clk/rockchip/rst-rk3588.c

31 	RK3588_CRU_RESET_OFFSET(SRST_CSIPHY0, 1, 7), // missing in TRM
61 	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO3_5, 4, 7),
69 	RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2VO1USB, 5, 7),
79 	RK3588_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
80 	RK3588_CRU_RESET_OFFSET(SRST_P_AUDIO_BIU, 7, 3),
81 	RK3588_CRU_RESET_OFFSET(SRST_H_I2S0_8CH, 7, 4),
82 	RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_TX, 7, 7),
83 	RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_RX, 7, 10),
84 	RK3588_CRU_RESET_OFFSET(SRST_P_ACDCDIG, 7, 11),
85 	RK3588_CRU_RESET_OFFSET(SRST_H_I2S2_2CH, 7, 12),
86 	RK3588_CRU_RESET_OFFSET(SRST_H_I2S3_2CH, 7, 13),
99 	RK3588_CRU_RESET_OFFSET(SRST_PDM1, 9, 7),
108 	RK3588_CRU_RESET_OFFSET(SRST_A_DMAC2, 10, 7),
126 	RK3588_CRU_RESET_OFFSET(SRST_I2C8, 11, 7),
143 	RK3588_CRU_RESET_OFFSET(SRST_P_UART6, 12, 7),
161 	RK3588_CRU_RESET_OFFSET(SRST_P_SPI1, 14, 7),
178 	RK3588_CRU_RESET_OFFSET(SRST_PWM2, 15, 7),
193 	RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER8, 16, 7),
211 	RK3588_CRU_RESET_OFFSET(SRST_P_DECOM, 17, 7),
245 	RK3588_CRU_RESET_OFFSET(SRST_SBR_CH0, 20, 7),
263 	RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH1, 21, 7),
277 	RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 22, 7),
288 	RK3588_CRU_RESET_OFFSET(SRST_SBR_CH2, 23, 7),
306 	RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH3, 24, 7),
320 	RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH2, 25, 7),
359 	RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 30, 7),
369 	RK3588_CRU_RESET_OFFSET(SRST_B_EMMC, 31, 7),
399 	RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PCIE, 34, 7),
404 	RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG2, 35, 7),
410 	RK3588_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 7),
426 	RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CA, 40, 7),
436 	RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_HEVC_CA, 41, 7),
443 	RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 42, 7),
460 	RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER_BIU, 44, 7),
478 	RK3588_CRU_RESET_OFFSET(SRST_H_RGA2, 45, 7),
504 	RK3588_CRU_RESET_OFFSET(SRST_A_VICAP, 49, 7),
515 	RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 50, 7),
523 	RK3588_CRU_RESET_OFFSET(SRST_CSIHOST3_VICAP, 51, 7),
532 	RK3588_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 52, 7),
547 	RK3588_CRU_RESET_OFFSET(SRST_DSIHOST1, 53, 7),
554 	RK3588_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 55, 7),
575 	RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF5_DP1, 57, 7),
600 	RK3588_CRU_RESET_OFFSET(SRST_HDMITX1_REF, 61, 7),
618 	RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF3, 63, 7),
638 	RK3588_CRU_RESET_OFFSET(SRST_M_I2S10_8CH_RX, 65, 7),
668 	RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 69, 7),
682 	RK3588_CRU_RESET_OFFSET(SRST_P_WDT, 70, 7),
696 	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_BOT_RIGHT, 72, 7),
714 	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1, 73, 7), // missing in TRM
739 	RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY1, 77, 7),
749 	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY2, 0, 7),
767 	RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 1, 7),
779 	RK3588_PMU1CRU_RESET_OFFSET(SRST_H_I2S1_8CH, 2, 7),
799 	RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_0, 4, 7),