39 #define WARN_DEBUG(x)	do { } while (0)
56 	0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
57 	0x9A0, 0x9A4, 0x9A8, 0x9AC,
61 	0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
62 	0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, 0x2E3C,
63 	0x2E40, 0x2E44, 0x2E48, 0x2E4C, 0x2E50, 0x2E54, 0x2E58, 0x2E5C,
64 	0x2E60, 0x2E64, 0x2E68, 0x2E6C, 0x2E70, 0x2E74,
72 	0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
73 	0x990, 0x994, 0x998, 0x99C,
77 	0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
78 	0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, 0x2D3C,
79 	0x2D40, 0x2D44, 0x2D48, 0x2D4C, 0x2D50, 0x2D54, 0x2D58, 0x2D5C,
80 	0x2D60, 0x2D64, 0x2D68, 0x2D6C, 0x2D70, 0x2D74,
89 	0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420,
90 	0x424, 0x428, 0x42C,
98 	0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
99 	0x920, 0x924, 0x928, 0x92C,
103 	0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C,
104 	0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, 0x2C3C,
105 	0x2C40, 0x2C44, 0x2C48, 0x2C4C, 0x2C50, 0x2C54, 0x2C58, 0x2C5C,
106 	0x2C60, 0x2C64, 0x2C68, 0x2C6C, 0x2C70, 0x2C74,
114 	0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,
115 	0x960, 0x964, 0x968, 0x96C,
119 	0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C,
120 	0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, 0x2CBC,
121 	0x2CC0, 0x2CC4, 0x2CC8, 0x2CCC, 0x2CD0, 0x2CD4, 0x2CD8, 0x2CDC,
122 	0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC, 0x2CF0, 0x2CF4,
229 		return 0;  in cpg_mstp_clock_endisable()
232 					  value, !(value & bitmask), 0, 10);  in cpg_mstp_clock_endisable()
282 	switch (clkspec->args[0]) {  in cpg_mssr_clk_src_twocell_get()
302 		if (range_check < 0 || idx >= priv->num_mod_clks) {  in cpg_mssr_clk_src_twocell_get()
311 		dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);  in cpg_mssr_clk_src_twocell_get()
320 			clkspec->args[0], clkspec->args[1], clk,  in cpg_mssr_clk_src_twocell_get()
361 			div *= (readl(priv->base + core->offset) & 0x3f) + 1;  in cpg_mssr_register_core_clk()
369 							parent_name, 0,  in cpg_mssr_register_core_clk()
375 		clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,  in cpg_mssr_register_core_clk()
447 	for (i = 0; i < info->num_crit_mod_clks; i++)  in cpg_mssr_register_mod_clk()
487 	switch (clkspec->args[0]) {  in cpg_mssr_is_pm_clk()
489 		for (i = 0; i < pd->num_core_pm_clks; i++)  in cpg_mssr_is_pm_clk()
508 	int i = 0;  in cpg_mssr_attach_dev()
525 	return 0;  in cpg_mssr_attach_dev()
542 	return 0;  in cpg_mssr_attach_dev()
569 	size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);  in cpg_mssr_add_clk_domain()
621 	return 0;  in cpg_mssr_reset()
634 	return 0;  in cpg_mssr_assert()
648 	return 0;  in cpg_mssr_deassert()
673 	unsigned int unpacked = reset_spec->args[0];  in cpg_mssr_reset_xlate()
697 	return 0;  in cpg_mssr_reset_controller_register()
873 		return 0;  in cpg_mssr_suspend_noirq()
876 	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {  in cpg_mssr_suspend_noirq()
887 	return 0;  in cpg_mssr_suspend_noirq()
899 		return 0;  in cpg_mssr_resume_noirq()
905 	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {  in cpg_mssr_resume_noirq()
934 						oldval, !(oldval & mask), 0, 10);  in cpg_mssr_resume_noirq()
936 			dev_warn(dev, "Failed to enable SMSTP%u[0x%x]\n", reg,  in cpg_mssr_resume_noirq()
940 	return 0;  in cpg_mssr_resume_noirq()
975 	priv->base = of_iomap(np, 0);  in cpg_mssr_common_init()
1003 	for (i = 0; i < nclks; i++)  in cpg_mssr_common_init()
1012 	return 0;  in cpg_mssr_common_init()
1032 	for (i = 0; i < info->num_early_core_clks; i++)  in cpg_mssr_early_init()
1036 	for (i = 0; i < info->num_early_mod_clks; i++)  in cpg_mssr_early_init()
1063 	for (i = 0; i < info->num_core_clks; i++)  in cpg_mssr_probe()
1066 	for (i = 0; i < info->num_mod_clks; i++)  in cpg_mssr_probe()
1082 		return 0;  in cpg_mssr_probe()
1088 	return 0;  in cpg_mssr_probe()
1112 	for (i = 0, j = 0; i < num_mod_clks && j < n; i++)  in mssr_mod_nullify()