Lines Matching +full:0 +full:x584
18 #define G3S_CPG_PL2_DDIV (0x204)
19 #define G3S_CPG_SDHI_DDIV (0x218)
20 #define G3S_CPG_PLL_DSEL (0x240)
21 #define G3S_CPG_SDHI_DSEL (0x244)
22 #define G3S_CLKDIVSTATUS (0x280)
23 #define G3S_CLKSELSTATUS (0x284)
27 #define G3S_DIV_SDHI0 DDIV_PACK(G3S_CPG_SDHI_DDIV, 0, 1)
32 #define G3S_DIVPL1A_STS DDIV_PACK(G3S_CLKDIVSTATUS, 0, 1)
48 #define G3S_SEL_SDHI0 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 0, 2)
100 { 0, 1 },
102 { 0, 0 },
106 { 0, 1 },
110 { 0, 0 },
114 { 0, 1 },
119 { 0, 0 },
127 static const u32 mtable_sd[] = { 0, 2, 3 };
128 static const u32 mtable_pll4[] = { 0, 1 };
136 DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8)),
150 mtable_sd, 0, NULL),
152 mtable_sd, 0, NULL),
154 mtable_sd, 0, NULL),
160 0, 0, 0, NULL),
162 dtable_1_32, 0, 0, 0, NULL),
177 dtable_1_32, 0, 0, 0, NULL),
180 dtable_1_32, 0, 0, 0, NULL),
182 dtable_1_32, 0, 0, 0, NULL),
192 DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0),
193 DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0),
194 DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1),
195 DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0),
196 DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0),
197 DEF_MOD("sdhi0_imclk2", R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1),
198 DEF_MOD("sdhi0_clk_hs", R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2),
199 DEF_MOD("sdhi0_aclk", R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3),
200 DEF_MOD("sdhi1_imclk", R9A08G045_SDHI1_IMCLK, CLK_SD1_DIV4, 0x554, 4),
201 DEF_MOD("sdhi1_imclk2", R9A08G045_SDHI1_IMCLK2, CLK_SD1_DIV4, 0x554, 5),
202 DEF_MOD("sdhi1_clk_hs", R9A08G045_SDHI1_CLK_HS, R9A08G045_CLK_SD1, 0x554, 6),
203 DEF_MOD("sdhi1_aclk", R9A08G045_SDHI1_ACLK, R9A08G045_CLK_P1, 0x554, 7),
204 DEF_MOD("sdhi2_imclk", R9A08G045_SDHI2_IMCLK, CLK_SD2_DIV4, 0x554, 8),
205 DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9),
206 DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10),
207 DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11),
208 DEF_COUPLED("eth0_axi", R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0),
209 DEF_COUPLED("eth0_chi", R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0),
210 DEF_MOD("eth0_refclk", R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8),
211 DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1),
212 DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1),
213 DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9),
214 DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),
215 DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
219 DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0),
220 DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1),
221 DEF_RST(R9A08G045_IA55_RESETN, 0x818, 0),
222 DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),
223 DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1),
224 DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),
225 DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0),
226 DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1),
227 DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0),
228 DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),
229 DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),
230 DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2),