clk/renesas/r9a07g043-cpg.c

18 #define CPG_PL2SDHI_DSEL	(0x218)
21 #define SEL_SDHI0		SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2)
71 	{0, 1},
75 	{0, 0},
79 	{0, 1},
84 	{0, 0},
101 	DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
140 		   mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
142 		   mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
150 				0x514, 0),
152 				0x518, 0),
154 				0x518, 1),
158 				0x518, 0),
160 				0x518, 1),
163 				0x52c, 0),
165 				0x52c, 1),
167 				0x534, 0),
169 				0x534, 1),
171 				0x534, 2),
173 				0x538, 0),
175 				0x548, 0),
177 				0x548, 1),
179 				0x550, 0),
181 				0x550, 1),
183 				0x554, 0),
185 				0x554, 1),
187 				0x554, 2),
189 				0x554, 3),
191 				0x554, 4),
193 				0x554, 5),
195 				0x554, 6),
197 				0x554, 7),
199 				0x570, 0),
201 				0x570, 1),
203 				0x570, 2),
205 				0x570, 3),
207 				0x570, 4),
209 				0x570, 5),
211 				0x570, 6),
213 				0x570, 7),
215 				0x578, 0),
217 				0x578, 1),
219 				0x578, 2),
221 				0x578, 3),
223 				0x57c, 0),
225 				0x57c, 0),
227 				0x57c, 1),
229 				0x57c, 1),
231 				0x580, 0),
233 				0x580, 1),
235 				0x580, 2),
237 				0x580, 3),
239 				0x584, 0),
241 				0x584, 1),
243 				0x584, 2),
245 				0x584, 3),
247 				0x584, 4),
249 				0x588, 0),
251 				0x588, 1),
253 				0x590, 0),
255 				0x590, 1),
257 				0x590, 2),
259 				0x594, 0),
261 				0x598, 0),
263 				0x5a8, 0),
265 				0x5a8, 1),
267 				0x5ac, 0),
272 	DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),
273 	DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),
274 	DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0),
277 	DEF_RST(R9A07G043_IAX45_RESETN, 0x818, 0),
279 	DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0),
280 	DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),
281 	DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0),
282 	DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
283 	DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
284 	DEF_RST(R9A07G043_MTU_X_PRESET_MTU3, 0x838, 0),
285 	DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),
286 	DEF_RST(R9A07G043_SPI_RST, 0x850, 0),
287 	DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
288 	DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
289 	DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0),
290 	DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1),
291 	DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2),
292 	DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3),
293 	DEF_RST(R9A07G043_USB_U2H0_HRESETN, 0x878, 0),
294 	DEF_RST(R9A07G043_USB_U2H1_HRESETN, 0x878, 1),
295 	DEF_RST(R9A07G043_USB_U2P_EXL_SYSRST, 0x878, 2),
296 	DEF_RST(R9A07G043_USB_PRESETN, 0x878, 3),
297 	DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0),
298 	DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1),
299 	DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0),
300 	DEF_RST(R9A07G043_I2C1_MRST, 0x880, 1),
301 	DEF_RST(R9A07G043_I2C2_MRST, 0x880, 2),
302 	DEF_RST(R9A07G043_I2C3_MRST, 0x880, 3),
303 	DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0),
304 	DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1),
305 	DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2),
306 	DEF_RST(R9A07G043_SCIF3_RST_SYSTEM_N, 0x884, 3),
307 	DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4),
308 	DEF_RST(R9A07G043_SCI0_RST, 0x888, 0),
309 	DEF_RST(R9A07G043_SCI1_RST, 0x888, 1),
310 	DEF_RST(R9A07G043_RSPI0_RST, 0x890, 0),
311 	DEF_RST(R9A07G043_RSPI1_RST, 0x890, 1),
312 	DEF_RST(R9A07G043_RSPI2_RST, 0x890, 2),
313 	DEF_RST(R9A07G043_CANFD_RSTP_N, 0x894, 0),
314 	DEF_RST(R9A07G043_CANFD_RSTC_N, 0x894, 1),
315 	DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0),
316 	DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1),
317 	DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2),
318 	DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0),
319 	DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1),
320 	DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0),