Lines Matching +full:0 +full:x160
99 DEF_GEN4_Z("z0", R8A779G0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 0),
148 DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
149 DEF_DIV6P1("csi", R8A779G0_CLK_CSI, CLK_PLL5_DIV4, 0x880),
151 DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),
153 DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, 0x870),
154 DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, 0x870),
155 DEF_DIV6P1("mso", R8A779G0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
252 * 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /16
253 * 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19
254 * 1 0 Prohibited setting
264 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
280 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); in r8a779g0_cpg_mssr_init()