clk/renesas/r8a77995-cpg-mssr.c

1 // SPDX-License-Identifier: GPL-2.0
3  * r8a77995 Clock Pulse Generator / Module Standby and Software Reset
7  * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
112 	DEF_BASE("rpc",        R8A77995_CLK_RPC,   CLK_TYPE_GEN3_RPC,   CLK_RPCSRC),
136 	DEF_MOD("sys-dmac2",		 217,	R8A77995_CLK_S3D1),
137 	DEF_MOD("sys-dmac1",		 218,	R8A77995_CLK_S3D1),
138 	DEF_MOD("sys-dmac0",		 219,	R8A77995_CLK_S3D1),
139 	DEF_MOD("sceg-pub",		 229,	R8A77995_CLK_CR),
146 	DEF_MOD("usb-dmac0",		 330,	R8A77995_CLK_S3D1),
147 	DEF_MOD("usb-dmac1",		 331,	R8A77995_CLK_S3D1),
149 	DEF_MOD("intc-ex",		 407,	R8A77995_CLK_CP),
150 	DEF_MOD("intc-ap",		 408,	R8A77995_CLK_S1D2),
180 	DEF_MOD("can-fd",		 914,	R8A77995_CLK_S3D2),
181 	DEF_MOD("can-if1",		 915,	R8A77995_CLK_S3D4),
182 	DEF_MOD("can-if0",		 916,	R8A77995_CLK_S3D4),
183 	DEF_MOD("rpc-if",		 917,	R8A77995_CLK_RPCD2),
189 	DEF_MOD("ssi-all",		1005,	R8A77995_CLK_S3D4),
192 	DEF_MOD("scu-all",		1017,	R8A77995_CLK_S3D4),
193 	DEF_MOD("scu-dvc1",		1018,	MOD_CLK_ID(1017)),
194 	DEF_MOD("scu-dvc0",		1019,	MOD_CLK_ID(1017)),
195 	DEF_MOD("scu-ctu1-mix1",	1020,	MOD_CLK_ID(1017)),
196 	DEF_MOD("scu-ctu0-mix0",	1021,	MOD_CLK_ID(1017)),
197 	DEF_MOD("scu-src6",		1025,	MOD_CLK_ID(1017)),
198 	DEF_MOD("scu-src5",		1026,	MOD_CLK_ID(1017)),
203 	MOD_CLK_ID(408),	/* INTC-AP (GIC) */
212  *--------------------------------------------------------------------
231 	if (error)  in r8a77995_cpg_mssr_init()