1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
33 	unsigned int reg;  member
67 	unsigned int shift, reg;  in r8a7740_cpg_register_clock()  local
121 		for (c = div4_clks; c->name; c++) {  in r8a7740_cpg_register_clock()
122 			if (!strcmp(name, c->name)) {  in r8a7740_cpg_register_clock()
125 				reg = c->reg;  in r8a7740_cpg_register_clock()
126 				shift = c->shift;  in r8a7740_cpg_register_clock()
130 		if (!c->name)  in r8a7740_cpg_register_clock()
131 			return ERR_PTR(-EINVAL);  in r8a7740_cpg_register_clock()
139 						  base + reg, shift, 4, 0,  in r8a7740_cpg_register_clock()
140 						  table, &cpg->lock);  in r8a7740_cpg_register_clock()
155 	num_clks = of_property_count_strings(np, "clock-output-names");  in r8a7740_cpg_clocks_init()
170 	spin_lock_init(&cpg->lock);  in r8a7740_cpg_clocks_init()
172 	cpg->data.clks = clks;  in r8a7740_cpg_clocks_init()
173 	cpg->data.clk_num = num_clks;  in r8a7740_cpg_clocks_init()
183 		of_property_read_string_index(np, "clock-output-names", i,  in r8a7740_cpg_clocks_init()
191 			cpg->data.clks[i] = clk;  in r8a7740_cpg_clocks_init()
194 	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);  in r8a7740_cpg_clocks_init()
196 CLK_OF_DECLARE(r8a7740_cpg_clks, "renesas,r8a7740-cpg-clocks",