1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2014  Ulrich Hecht
8 #include <linux/clk-provider.h>
23 #define CPG_FRQCRA	0x00
24 #define CPG_FRQCRB	0x04
25 #define CPG_PLLC2CR	0x2c
26 #define CPG_USBCKCR	0x8c
27 #define CPG_FRQCRC	0xe0
29 #define CLK_ENABLE_ON_INIT BIT(0)
32 	const char *name;  member
63 			   void __iomem *base, const char *name)  in r8a7740_cpg_register_clock()  argument
71 	if (!strcmp(name, "r")) {  in r8a7740_cpg_register_clock()
88 	} else if (!strcmp(name, "system")) {  in r8a7740_cpg_register_clock()
92 	} else if (!strcmp(name, "pllc0")) {  in r8a7740_cpg_register_clock()
101 	} else if (!strcmp(name, "pllc1")) {  in r8a7740_cpg_register_clock()
106 	} else if (!strcmp(name, "pllc2")) {  in r8a7740_cpg_register_clock()
110 	} else if (!strcmp(name, "usb24s")) {  in r8a7740_cpg_register_clock()
120 		struct div4_clk *c;  in r8a7740_cpg_register_clock()  local
121 		for (c = div4_clks; c->name; c++) {  in r8a7740_cpg_register_clock()
122 			if (!strcmp(name, c->name)) {  in r8a7740_cpg_register_clock()
125 				reg = c->reg;  in r8a7740_cpg_register_clock()
126 				shift = c->shift;  in r8a7740_cpg_register_clock()
130 		if (!c->name)  in r8a7740_cpg_register_clock()
131 			return ERR_PTR(-EINVAL);  in r8a7740_cpg_register_clock()
135 		return clk_register_fixed_factor(NULL, name, parent_name, 0,  in r8a7740_cpg_register_clock()
138 		return clk_register_divider_table(NULL, name, parent_name, 0,  in r8a7740_cpg_register_clock()
140 						  table, &cpg->lock);  in r8a7740_cpg_register_clock()
155 	num_clks = of_property_count_strings(np, "clock-output-names");  in r8a7740_cpg_clocks_init()
170 	spin_lock_init(&cpg->lock);  in r8a7740_cpg_clocks_init()
172 	cpg->data.clks = clks;  in r8a7740_cpg_clocks_init()
173 	cpg->data.clk_num = num_clks;  in r8a7740_cpg_clocks_init()
180 		const char *name;  in r8a7740_cpg_clocks_init()  local
183 		of_property_read_string_index(np, "clock-output-names", i,  in r8a7740_cpg_clocks_init()
184 					      &name);  in r8a7740_cpg_clocks_init()
186 		clk = r8a7740_cpg_register_clock(np, cpg, base, name);  in r8a7740_cpg_clocks_init()
189 			       __func__, np, name, PTR_ERR(clk));  in r8a7740_cpg_clocks_init()
191 			cpg->data.clks[i] = clk;  in r8a7740_cpg_clocks_init()
194 	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);  in r8a7740_cpg_clocks_init()
196 CLK_OF_DECLARE(r8a7740_cpg_clks, "renesas,r8a7740-cpg-clocks",