Lines Matching +full:0 +full:x4038
45 .l_reg = 0x0004,
46 .m_reg = 0x0008,
47 .n_reg = 0x000c,
48 .config_reg = 0x0014,
49 .mode_reg = 0x0000,
50 .status_reg = 0x001c,
63 .enable_reg = 0x0100,
64 .enable_mask = BIT(0),
76 .l_reg = 0x0044,
77 .m_reg = 0x0048,
78 .n_reg = 0x004c,
79 .config_reg = 0x0050,
80 .mode_reg = 0x0040,
81 .status_reg = 0x005c,
94 .enable_reg = 0x0100,
107 .l_reg = 0x4104,
108 .m_reg = 0x4108,
109 .n_reg = 0x410c,
110 .config_reg = 0x4110,
111 .mode_reg = 0x4100,
112 .status_reg = 0x411c,
124 .l_reg = 0x0084,
125 .m_reg = 0x0088,
126 .n_reg = 0x008c,
127 .config_reg = 0x0090,
128 .mode_reg = 0x0080,
129 .status_reg = 0x009c,
142 { P_XO, 0 },
156 { P_XO, 0 },
174 { P_XO, 0 },
190 { P_XO, 0 },
206 { P_XO, 0 },
224 { P_XO, 0 },
242 { P_XO, 0 },
260 .cmd_rcgr = 0x5000,
272 F(19200000, P_XO, 1, 0, 0),
273 F(37500000, P_GPLL0, 16, 0, 0),
274 F(50000000, P_GPLL0, 12, 0, 0),
275 F(75000000, P_GPLL0, 8, 0, 0),
276 F(100000000, P_GPLL0, 6, 0, 0),
277 F(150000000, P_GPLL0, 4, 0, 0),
278 F(200000000, P_MMPLL0, 4, 0, 0),
279 F(266666666, P_MMPLL0, 3, 0, 0),
284 F( 19200000, P_XO, 1, 0, 0),
285 F( 37500000, P_GPLL0, 16, 0, 0),
286 F( 50000000, P_GPLL0, 12, 0, 0),
287 F( 75000000, P_GPLL0, 8, 0, 0),
288 F(100000000, P_GPLL0, 6, 0, 0),
289 F(150000000, P_GPLL0, 4, 0, 0),
290 F(291750000, P_MMPLL1, 4, 0, 0),
291 F(400000000, P_MMPLL0, 2, 0, 0),
292 F(466800000, P_MMPLL1, 2.5, 0, 0),
296 .cmd_rcgr = 0x5040,
309 F( 19200000, P_XO, 1, 0, 0),
310 F( 37500000, P_GPLL0, 16, 0, 0),
311 F( 50000000, P_GPLL0, 12, 0, 0),
312 F( 75000000, P_GPLL0, 8, 0, 0),
313 F(100000000, P_GPLL0, 6, 0, 0),
314 F(150000000, P_GPLL0, 4, 0, 0),
315 F(291750000, P_MMPLL1, 4, 0, 0),
316 F(400000000, P_MMPLL0, 2, 0, 0),
320 .cmd_rcgr = 0x5090,
333 F(100000000, P_GPLL0, 6, 0, 0),
334 F(200000000, P_MMPLL0, 4, 0, 0),
339 .cmd_rcgr = 0x3090,
352 .cmd_rcgr = 0x3100,
365 .cmd_rcgr = 0x3160,
378 .cmd_rcgr = 0x31c0,
391 F(37500000, P_GPLL0, 16, 0, 0),
392 F(50000000, P_GPLL0, 12, 0, 0),
393 F(60000000, P_GPLL0, 10, 0, 0),
394 F(80000000, P_GPLL0, 7.5, 0, 0),
395 F(100000000, P_GPLL0, 6, 0, 0),
396 F(109090000, P_GPLL0, 5.5, 0, 0),
397 F(133330000, P_GPLL0, 4.5, 0, 0),
398 F(150000000, P_GPLL0, 4, 0, 0),
399 F(200000000, P_GPLL0, 3, 0, 0),
400 F(228570000, P_MMPLL0, 3.5, 0, 0),
401 F(266670000, P_MMPLL0, 3, 0, 0),
402 F(320000000, P_MMPLL0, 2.5, 0, 0),
403 F(400000000, P_MMPLL0, 2, 0, 0),
408 F(37500000, P_GPLL0, 16, 0, 0),
409 F(50000000, P_GPLL0, 12, 0, 0),
410 F(60000000, P_GPLL0, 10, 0, 0),
411 F(80000000, P_GPLL0, 7.5, 0, 0),
412 F(100000000, P_GPLL0, 6, 0, 0),
413 F(109090000, P_GPLL0, 5.5, 0, 0),
414 F(133330000, P_GPLL0, 4.5, 0, 0),
415 F(200000000, P_GPLL0, 3, 0, 0),
416 F(228570000, P_MMPLL0, 3.5, 0, 0),
417 F(266670000, P_MMPLL0, 3, 0, 0),
418 F(320000000, P_MMPLL0, 2.5, 0, 0),
419 F(400000000, P_MMPLL0, 2, 0, 0),
420 F(465000000, P_MMPLL3, 2, 0, 0),
425 .cmd_rcgr = 0x3600,
438 .cmd_rcgr = 0x3620,
451 F(37500000, P_GPLL0, 16, 0, 0),
452 F(60000000, P_GPLL0, 10, 0, 0),
453 F(75000000, P_GPLL0, 8, 0, 0),
454 F(92310000, P_GPLL0, 6.5, 0, 0),
455 F(100000000, P_GPLL0, 6, 0, 0),
456 F(133330000, P_MMPLL0, 6, 0, 0),
457 F(177780000, P_MMPLL0, 4.5, 0, 0),
458 F(200000000, P_MMPLL0, 4, 0, 0),
463 F(37500000, P_GPLL0, 16, 0, 0),
464 F(60000000, P_GPLL0, 10, 0, 0),
465 F(75000000, P_GPLL0, 8, 0, 0),
466 F(85710000, P_GPLL0, 7, 0, 0),
467 F(100000000, P_GPLL0, 6, 0, 0),
468 F(133330000, P_MMPLL0, 6, 0, 0),
469 F(160000000, P_MMPLL0, 5, 0, 0),
470 F(200000000, P_MMPLL0, 4, 0, 0),
471 F(228570000, P_MMPLL0, 3.5, 0, 0),
472 F(240000000, P_GPLL0, 2.5, 0, 0),
473 F(266670000, P_MMPLL0, 3, 0, 0),
474 F(320000000, P_MMPLL0, 2.5, 0, 0),
479 .cmd_rcgr = 0x2040,
492 F(75000000, P_GPLL0, 8, 0, 0),
493 F(133330000, P_GPLL0, 4.5, 0, 0),
494 F(200000000, P_GPLL0, 3, 0, 0),
495 F(228570000, P_MMPLL0, 3.5, 0, 0),
496 F(266670000, P_MMPLL0, 3, 0, 0),
497 F(320000000, P_MMPLL0, 2.5, 0, 0),
502 .cmd_rcgr = 0x3500,
515 .cmd_rcgr = 0x3520,
528 .cmd_rcgr = 0x3540,
541 .cmd_rcgr = 0x2000,
555 .cmd_rcgr = 0x2020,
569 F(66700000, P_GPLL0, 9, 0, 0),
570 F(100000000, P_GPLL0, 6, 0, 0),
571 F(133330000, P_MMPLL0, 6, 0, 0),
572 F(160000000, P_MMPLL0, 5, 0, 0),
577 F(50000000, P_GPLL0, 12, 0, 0),
578 F(100000000, P_GPLL0, 6, 0, 0),
579 F(133330000, P_MMPLL0, 6, 0, 0),
580 F(200000000, P_MMPLL0, 4, 0, 0),
581 F(266670000, P_MMPLL0, 3, 0, 0),
582 F(465000000, P_MMPLL3, 2, 0, 0),
587 .cmd_rcgr = 0x1000,
601 F(19200000, P_XO, 1, 0, 0),
606 .cmd_rcgr = 0x3300,
629 .cmd_rcgr = 0x3420,
643 .cmd_rcgr = 0x3450,
657 F(19200000, P_XO, 1, 0, 0),
659 F(66670000, P_GPLL0, 9, 0, 0),
664 F(4800000, P_XO, 4, 0, 0),
667 F(9600000, P_XO, 2, 0, 0),
669 F(19200000, P_XO, 1, 0, 0),
672 F(48000000, P_GPLL0, 12.5, 0, 0),
673 F(64000000, P_MMPLL0, 12.5, 0, 0),
674 F(66670000, P_GPLL0, 9, 0, 0),
679 .cmd_rcgr = 0x3360,
692 .cmd_rcgr = 0x3390,
705 .cmd_rcgr = 0x33c0,
718 .cmd_rcgr = 0x33f0,
731 F(100000000, P_GPLL0, 6, 0, 0),
732 F(200000000, P_MMPLL0, 4, 0, 0),
737 .cmd_rcgr = 0x3000,
750 .cmd_rcgr = 0x3030,
763 .cmd_rcgr = 0x3060,
776 F(133330000, P_GPLL0, 4.5, 0, 0),
777 F(150000000, P_GPLL0, 4, 0, 0),
778 F(266670000, P_MMPLL0, 3, 0, 0),
779 F(320000000, P_MMPLL0, 2.5, 0, 0),
780 F(400000000, P_MMPLL0, 2, 0, 0),
785 F(133330000, P_GPLL0, 4.5, 0, 0),
786 F(266670000, P_MMPLL0, 3, 0, 0),
787 F(320000000, P_MMPLL0, 2.5, 0, 0),
788 F(400000000, P_MMPLL0, 2, 0, 0),
789 F(465000000, P_MMPLL3, 2, 0, 0),
794 .cmd_rcgr = 0x3640,
812 .cmd_rcgr = 0x2120,
826 .cmd_rcgr = 0x2140,
840 F(19200000, P_XO, 1, 0, 0),
845 .cmd_rcgr = 0x20e0,
858 F(135000000, P_EDPLINK, 2, 0, 0),
859 F(270000000, P_EDPLINK, 11, 0, 0),
864 .cmd_rcgr = 0x20c0,
883 .cmd_rcgr = 0x20a0,
897 F(19200000, P_XO, 1, 0, 0),
902 .cmd_rcgr = 0x2160,
915 .cmd_rcgr = 0x2180,
933 .cmd_rcgr = 0x2060,
947 F(19200000, P_XO, 1, 0, 0),
952 .cmd_rcgr = 0x2100,
965 F(19200000, P_XO, 1, 0, 0),
970 .cmd_rcgr = 0x2080,
983 .halt_reg = 0x3348,
985 .enable_reg = 0x3348,
986 .enable_mask = BIT(0),
999 .halt_reg = 0x3344,
1001 .enable_reg = 0x3344,
1002 .enable_mask = BIT(0),
1016 .halt_reg = 0x30bc,
1018 .enable_reg = 0x30bc,
1019 .enable_mask = BIT(0),
1032 .halt_reg = 0x30b4,
1034 .enable_reg = 0x30b4,
1035 .enable_mask = BIT(0),
1049 .halt_reg = 0x30c4,
1051 .enable_reg = 0x30c4,
1052 .enable_mask = BIT(0),
1066 .halt_reg = 0x30e4,
1068 .enable_reg = 0x30e4,
1069 .enable_mask = BIT(0),
1083 .halt_reg = 0x30d4,
1085 .enable_reg = 0x30d4,
1086 .enable_mask = BIT(0),
1100 .halt_reg = 0x3128,
1102 .enable_reg = 0x3128,
1103 .enable_mask = BIT(0),
1116 .halt_reg = 0x3124,
1118 .enable_reg = 0x3124,
1119 .enable_mask = BIT(0),
1133 .halt_reg = 0x3134,
1135 .enable_reg = 0x3134,
1136 .enable_mask = BIT(0),
1150 .halt_reg = 0x3154,
1152 .enable_reg = 0x3154,
1153 .enable_mask = BIT(0),
1167 .halt_reg = 0x3144,
1169 .enable_reg = 0x3144,
1170 .enable_mask = BIT(0),
1184 .halt_reg = 0x3188,
1186 .enable_reg = 0x3188,
1187 .enable_mask = BIT(0),
1200 .halt_reg = 0x3184,
1202 .enable_reg = 0x3184,
1203 .enable_mask = BIT(0),
1217 .halt_reg = 0x3194,
1219 .enable_reg = 0x3194,
1220 .enable_mask = BIT(0),
1234 .halt_reg = 0x31b4,
1236 .enable_reg = 0x31b4,
1237 .enable_mask = BIT(0),
1251 .halt_reg = 0x31a4,
1253 .enable_reg = 0x31a4,
1254 .enable_mask = BIT(0),
1268 .halt_reg = 0x31e8,
1270 .enable_reg = 0x31e8,
1271 .enable_mask = BIT(0),
1284 .halt_reg = 0x31e4,
1286 .enable_reg = 0x31e4,
1287 .enable_mask = BIT(0),
1301 .halt_reg = 0x31f4,
1303 .enable_reg = 0x31f4,
1304 .enable_mask = BIT(0),
1318 .halt_reg = 0x3214,
1320 .enable_reg = 0x3214,
1321 .enable_mask = BIT(0),
1335 .halt_reg = 0x3204,
1337 .enable_reg = 0x3204,
1338 .enable_mask = BIT(0),
1352 .halt_reg = 0x3704,
1354 .enable_reg = 0x3704,
1355 .enable_mask = BIT(0),
1369 .halt_reg = 0x3714,
1371 .enable_reg = 0x3714,
1372 .enable_mask = BIT(0),
1386 .halt_reg = 0x3444,
1388 .enable_reg = 0x3444,
1389 .enable_mask = BIT(0),
1403 .halt_reg = 0x3474,
1405 .enable_reg = 0x3474,
1406 .enable_mask = BIT(0),
1420 .halt_reg = 0x3224,
1422 .enable_reg = 0x3224,
1423 .enable_mask = BIT(0),
1436 .halt_reg = 0x35a8,
1438 .enable_reg = 0x35a8,
1439 .enable_mask = BIT(0),
1453 .halt_reg = 0x35ac,
1455 .enable_reg = 0x35ac,
1456 .enable_mask = BIT(0),
1470 .halt_reg = 0x35b0,
1472 .enable_reg = 0x35b0,
1473 .enable_mask = BIT(0),
1487 .halt_reg = 0x35b4,
1489 .enable_reg = 0x35b4,
1490 .enable_mask = BIT(0),
1503 .halt_reg = 0x35b8,
1505 .enable_reg = 0x35b8,
1506 .enable_mask = BIT(0),
1519 .halt_reg = 0x35bc,
1521 .enable_reg = 0x35bc,
1522 .enable_mask = BIT(0),
1536 .halt_reg = 0x3384,
1538 .enable_reg = 0x3384,
1539 .enable_mask = BIT(0),
1553 .halt_reg = 0x33b4,
1555 .enable_reg = 0x33b4,
1556 .enable_mask = BIT(0),
1570 .halt_reg = 0x33e4,
1572 .enable_reg = 0x33e4,
1573 .enable_mask = BIT(0),
1587 .halt_reg = 0x3414,
1589 .enable_reg = 0x3414,
1590 .enable_mask = BIT(0),
1604 .halt_reg = 0x3494,
1606 .enable_reg = 0x3494,
1607 .enable_mask = BIT(0),
1620 .halt_reg = 0x3024,
1622 .enable_reg = 0x3024,
1623 .enable_mask = BIT(0),
1637 .halt_reg = 0x3054,
1639 .enable_reg = 0x3054,
1640 .enable_mask = BIT(0),
1654 .halt_reg = 0x3084,
1656 .enable_reg = 0x3084,
1657 .enable_mask = BIT(0),
1671 .halt_reg = 0x3484,
1673 .enable_reg = 0x3484,
1674 .enable_mask = BIT(0),
1687 .halt_reg = 0x36b4,
1689 .enable_reg = 0x36b4,
1690 .enable_mask = BIT(0),
1703 .halt_reg = 0x36b0,
1705 .enable_reg = 0x36b0,
1706 .enable_mask = BIT(0),
1720 .halt_reg = 0x36a8,
1722 .enable_reg = 0x36a8,
1723 .enable_mask = BIT(0),
1737 .halt_reg = 0x36ac,
1739 .enable_reg = 0x36ac,
1740 .enable_mask = BIT(0),
1754 .halt_reg = 0x36b8,
1756 .enable_reg = 0x36b8,
1757 .enable_mask = BIT(0),
1770 .halt_reg = 0x36bc,
1772 .enable_reg = 0x36bc,
1773 .enable_mask = BIT(0),
1786 .halt_reg = 0x36c0,
1788 .enable_reg = 0x36c0,
1789 .enable_mask = BIT(0),
1803 .halt_reg = 0x2308,
1805 .enable_reg = 0x2308,
1806 .enable_mask = BIT(0),
1819 .halt_reg = 0x2310,
1821 .enable_reg = 0x2310,
1822 .enable_mask = BIT(0),
1836 .halt_reg = 0x233c,
1838 .enable_reg = 0x233c,
1839 .enable_mask = BIT(0),
1853 .halt_reg = 0x2340,
1855 .enable_reg = 0x2340,
1856 .enable_mask = BIT(0),
1870 .halt_reg = 0x2334,
1872 .enable_reg = 0x2334,
1873 .enable_mask = BIT(0),
1887 .halt_reg = 0x2330,
1889 .enable_reg = 0x2330,
1890 .enable_mask = BIT(0),
1904 .halt_reg = 0x232c,
1906 .enable_reg = 0x232c,
1907 .enable_mask = BIT(0),
1921 .halt_reg = 0x2344,
1923 .enable_reg = 0x2344,
1924 .enable_mask = BIT(0),
1938 .halt_reg = 0x2348,
1940 .enable_reg = 0x2348,
1941 .enable_mask = BIT(0),
1955 .halt_reg = 0x2324,
1957 .enable_reg = 0x2324,
1958 .enable_mask = BIT(0),
1972 .halt_reg = 0x230c,
1974 .enable_reg = 0x230c,
1975 .enable_mask = BIT(0),
1988 .halt_reg = 0x2338,
1990 .enable_reg = 0x2338,
1991 .enable_mask = BIT(0),
2005 .halt_reg = 0x231c,
2007 .enable_reg = 0x231c,
2008 .enable_mask = BIT(0),
2022 .halt_reg = 0x2320,
2024 .enable_reg = 0x2320,
2025 .enable_mask = BIT(0),
2039 .halt_reg = 0x2314,
2041 .enable_reg = 0x2314,
2042 .enable_mask = BIT(0),
2056 .halt_reg = 0x2318,
2058 .enable_reg = 0x2318,
2059 .enable_mask = BIT(0),
2073 .halt_reg = 0x2328,
2075 .enable_reg = 0x2328,
2076 .enable_mask = BIT(0),
2090 .halt_reg = 0x502c,
2092 .enable_reg = 0x502c,
2093 .enable_mask = BIT(0),
2106 .halt_reg = 0x5024,
2108 .enable_reg = 0x5024,
2109 .enable_mask = BIT(0),
2123 .halt_reg = 0x5028,
2125 .enable_reg = 0x5028,
2126 .enable_mask = BIT(0),
2140 .halt_reg = 0x506c,
2142 .enable_reg = 0x506c,
2143 .enable_mask = BIT(0),
2157 .halt_reg = 0x5064,
2159 .enable_reg = 0x5064,
2160 .enable_mask = BIT(0),
2174 .halt_reg = 0x4058,
2176 .enable_reg = 0x4058,
2177 .enable_mask = BIT(0),
2191 .halt_reg = 0x50b4,
2193 .enable_reg = 0x50b4,
2194 .enable_mask = BIT(0),
2208 .halt_reg = 0x4028,
2210 .enable_reg = 0x4028,
2211 .enable_mask = BIT(0),
2225 .halt_reg = 0x403c,
2227 .enable_reg = 0x403c,
2228 .enable_mask = BIT(0),
2241 .halt_reg = 0x4038,
2243 .enable_reg = 0x4038,
2244 .enable_mask = BIT(0),
2257 .halt_reg = 0x1030,
2259 .enable_reg = 0x1030,
2260 .enable_mask = BIT(0),
2273 .halt_reg = 0x1034,
2275 .enable_reg = 0x1034,
2276 .enable_mask = BIT(0),
2289 .halt_reg = 0x1038,
2291 .enable_reg = 0x1038,
2292 .enable_mask = BIT(0),
2306 .halt_reg = 0x1028,
2308 .enable_reg = 0x1028,
2309 .enable_mask = BIT(0),
2326 .vco_val = 0x0,
2327 .vco_mask = 0x3 << 20,
2328 .pre_div_val = 0x0,
2329 .pre_div_mask = 0x7 << 12,
2330 .post_div_val = 0x0,
2331 .post_div_mask = 0x3 << 8,
2333 .main_output_mask = BIT(0),
2340 .vco_val = 0x0,
2341 .vco_mask = 0x3 << 20,
2342 .pre_div_val = 0x0,
2343 .pre_div_mask = 0x7 << 12,
2344 .post_div_val = 0x0,
2345 .post_div_mask = 0x3 << 8,
2347 .main_output_mask = BIT(0),
2352 .gdscr = 0x1024,
2353 .cxcs = (unsigned int []){ 0x1028 },
2364 .gdscr = 0x2304,
2365 .cxcs = (unsigned int []){ 0x231c, 0x2320 },
2374 .gdscr = 0x35a4,
2375 .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 },
2384 .gdscr = 0x36a4,
2385 .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 },
2394 .gdscr = 0x4024,
2395 .cxcs = (unsigned int []){ 0x4028 },
2404 .gdscr = 0x4034,
2413 .gdscr = 0x4034,
2414 .cxcs = (unsigned int []){ 0x4028 },
2499 [SPDM_RESET] = { 0x0200 },
2500 [SPDM_RM_RESET] = { 0x0300 },
2501 [VENUS0_RESET] = { 0x1020 },
2502 [MDSS_RESET] = { 0x2300 },
2517 .max_register = 0x5104,
2658 [SPDM_RESET] = { 0x0200 },
2659 [SPDM_RM_RESET] = { 0x0300 },
2660 [VENUS0_RESET] = { 0x1020 },
2661 [MDSS_RESET] = { 0x2300 },
2662 [CAMSS_PHY0_RESET] = { 0x3020 },
2663 [CAMSS_PHY1_RESET] = { 0x3050 },
2664 [CAMSS_PHY2_RESET] = { 0x3080 },
2665 [CAMSS_CSI0_RESET] = { 0x30b0 },
2666 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
2667 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
2668 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
2669 [CAMSS_CSI1_RESET] = { 0x3120 },
2670 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
2671 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
2672 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
2673 [CAMSS_CSI2_RESET] = { 0x3180 },
2674 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
2675 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
2676 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
2677 [CAMSS_CSI3_RESET] = { 0x31e0 },
2678 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
2679 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
2680 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
2681 [CAMSS_ISPIF_RESET] = { 0x3220 },
2682 [CAMSS_CCI_RESET] = { 0x3340 },
2683 [CAMSS_MCLK0_RESET] = { 0x3380 },
2684 [CAMSS_MCLK1_RESET] = { 0x33b0 },
2685 [CAMSS_MCLK2_RESET] = { 0x33e0 },
2686 [CAMSS_MCLK3_RESET] = { 0x3410 },
2687 [CAMSS_GP0_RESET] = { 0x3440 },
2688 [CAMSS_GP1_RESET] = { 0x3470 },
2689 [CAMSS_TOP_RESET] = { 0x3480 },
2690 [CAMSS_MICRO_RESET] = { 0x3490 },
2691 [CAMSS_JPEG_RESET] = { 0x35a0 },
2692 [CAMSS_VFE_RESET] = { 0x36a0 },
2693 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
2694 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
2695 [OXILI_RESET] = { 0x4020 },
2696 [OXILICX_RESET] = { 0x4030 },
2697 [OCMEMCX_RESET] = { 0x4050 },
2698 [MMSS_RBCRP_RESET] = { 0x4080 },
2699 [MMSSNOCAHB_RESET] = { 0x5020 },
2700 [MMSSNOCAXI_RESET] = { 0x5060 },
2701 [OCMEMNOC_RESET] = { 0x50b0 },
2717 .max_register = 0x5104,