Lines Matching +full:0 +full:x37000
35 .offset = 0x0,
38 .enable_reg = 0x52010,
39 .enable_mask = BIT(0),
52 { 0x1, 2 },
57 .offset = 0x0,
74 { 0x3, 3 },
79 .offset = 0x0,
96 .offset = 0x6000,
99 .enable_reg = 0x52010,
113 { 0x1, 2 },
118 .offset = 0x6000,
135 .offset = 0x7000,
138 .enable_reg = 0x52010,
152 { P_BI_TCXO, 0 },
166 { P_BI_TCXO, 0 },
176 { P_BI_TCXO, 0 },
186 { P_BI_TCXO, 0 },
198 { P_BI_TCXO, 0 },
212 { P_BI_TCXO, 0 },
222 { P_BI_TCXO, 0 },
234 { P_BI_TCXO, 0 },
246 .reg = 0x4514C,
247 .shift = 0,
260 .reg = 0x4ce00,
261 .shift = 0,
274 F(19200000, P_BI_TCXO, 1, 0, 0),
279 .cmd_rcgr = 0x30014,
280 .mnd_width = 0,
293 F(19200000, P_BI_TCXO, 1, 0, 0),
294 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
295 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
296 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
297 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
302 .cmd_rcgr = 0x37004,
316 .cmd_rcgr = 0x38004,
330 .cmd_rcgr = 0x39004,
344 F(19200000, P_BI_TCXO, 1, 0, 0),
345 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
350 .cmd_rcgr = 0x23010,
351 .mnd_width = 0,
366 F(19200000, P_BI_TCXO, 1, 0, 0),
371 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
374 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
378 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
379 F(128000000, P_GPLL6_OUT_EVEN, 3, 0, 0),
391 .cmd_rcgr = 0x21148,
407 .cmd_rcgr = 0x21278,
423 .cmd_rcgr = 0x213a8,
439 .cmd_rcgr = 0x214d8,
455 .cmd_rcgr = 0x21608,
471 .cmd_rcgr = 0x21738,
487 .cmd_rcgr = 0x22018,
503 .cmd_rcgr = 0x22148,
519 .cmd_rcgr = 0x22278,
535 .cmd_rcgr = 0x223a8,
551 .cmd_rcgr = 0x224d8,
567 .cmd_rcgr = 0x22608,
578 F(19200000, P_BI_TCXO, 1, 0, 0),
580 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
581 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
582 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
583 F(192000000, P_GPLL6_OUT_EVEN, 2, 0, 0),
584 F(384000000, P_GPLL6_OUT_EVEN, 1, 0, 0),
589 .cmd_rcgr = 0x4b024,
603 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
604 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
605 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
610 .cmd_rcgr = 0x4b00c,
611 .mnd_width = 0,
625 F(9600000, P_BI_TCXO, 2, 0, 0),
626 F(19200000, P_BI_TCXO, 1, 0, 0),
627 F(25000000, P_GPLL0_OUT_ODD, 8, 0, 0),
628 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
629 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
630 F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
635 .cmd_rcgr = 0x2000c,
650 F(25000000, P_GPLL0_OUT_ODD, 8, 0, 0),
651 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
652 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
653 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
654 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
659 .cmd_rcgr = 0x3a01c,
673 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
674 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
675 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
676 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
681 .cmd_rcgr = 0x3a048,
682 .mnd_width = 0,
695 F(9600000, P_BI_TCXO, 2, 0, 0),
696 F(19200000, P_BI_TCXO, 1, 0, 0),
701 .cmd_rcgr = 0x3a0b0,
702 .mnd_width = 0,
716 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
717 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
718 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
723 .cmd_rcgr = 0x3a060,
724 .mnd_width = 0,
737 F(66666667, P_GPLL0_OUT_ODD, 3, 0, 0),
738 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
739 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
740 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
745 .cmd_rcgr = 0x1a01c,
759 F(19200000, P_BI_TCXO, 1, 0, 0),
764 .cmd_rcgr = 0x1a034,
765 .mnd_width = 0,
779 .cmd_rcgr = 0x1a060,
780 .mnd_width = 0,
793 .halt_reg = 0x3e014,
795 .hwcg_reg = 0x3e014,
798 .enable_reg = 0x3e014,
799 .enable_mask = BIT(0),
813 .halt_reg = 0x3e014,
815 .hwcg_reg = 0x3e014,
818 .enable_reg = 0x3e014,
833 .halt_reg = 0x3e014,
835 .hwcg_reg = 0x3e014,
838 .enable_reg = 0x3e014,
853 .halt_reg = 0x3e010,
855 .hwcg_reg = 0x3e010,
858 .enable_reg = 0x3e010,
859 .enable_mask = BIT(0),
873 .halt_reg = 0x26004,
875 .hwcg_reg = 0x26004,
878 .enable_reg = 0x52000,
888 .halt_reg = 0x17008,
890 .hwcg_reg = 0x17008,
893 .enable_reg = 0x17008,
894 .enable_mask = BIT(0),
904 .halt_reg = 0x17018,
906 .hwcg_reg = 0x17018,
909 .enable_reg = 0x17018,
910 .enable_mask = BIT(0),
919 .halt_reg = 0x17078,
921 .hwcg_reg = 0x17078,
924 .enable_reg = 0x17078,
925 .enable_mask = BIT(0),
934 .halt_reg = 0x17024,
936 .hwcg_reg = 0x17024,
939 .enable_reg = 0x17024,
940 .enable_mask = BIT(0),
949 .halt_reg = 0x17030,
952 .enable_reg = 0x17030,
953 .enable_mask = BIT(0),
963 .halt_reg = 0x2b00c,
965 .hwcg_reg = 0x2b00c,
968 .enable_reg = 0x52008,
978 .halt_reg = 0x2b008,
981 .enable_reg = 0x52008,
991 .halt_reg = 0x2b004,
994 .enable_reg = 0x52008,
1004 .halt_reg = 0x1101c,
1006 .hwcg_reg = 0x1101c,
1009 .enable_reg = 0x1101c,
1010 .enable_mask = BIT(0),
1024 .halt_reg = 0x30000,
1026 .hwcg_reg = 0x30000,
1029 .enable_reg = 0x52008,
1044 .halt_reg = 0x30004,
1046 .hwcg_reg = 0x30004,
1049 .enable_reg = 0x52008,
1060 .halt_reg = 0x30008,
1063 .enable_reg = 0x30008,
1064 .enable_mask = BIT(0),
1073 .halt_reg = 0x2d038,
1075 .hwcg_reg = 0x2d038,
1078 .enable_reg = 0x2d038,
1079 .enable_mask = BIT(0),
1088 .halt_reg = 0x1700c,
1090 .hwcg_reg = 0x1700c,
1093 .enable_reg = 0x1700c,
1094 .enable_mask = BIT(0),
1104 .halt_reg = 0x1701c,
1106 .hwcg_reg = 0x1701c,
1109 .enable_reg = 0x1701c,
1110 .enable_mask = BIT(0),
1119 .halt_reg = 0x17074,
1121 .hwcg_reg = 0x17074,
1124 .enable_reg = 0x17074,
1125 .enable_mask = BIT(0),
1134 .halt_reg = 0x17070,
1136 .hwcg_reg = 0x17070,
1139 .enable_reg = 0x17070,
1140 .enable_mask = BIT(0),
1152 .enable_reg = 0x52000,
1166 .halt_reg = 0x17028,
1168 .hwcg_reg = 0x17028,
1171 .enable_reg = 0x17028,
1172 .enable_mask = BIT(0),
1181 .halt_reg = 0x17034,
1184 .enable_reg = 0x17034,
1185 .enable_mask = BIT(0),
1194 .halt_reg = 0x37000,
1197 .enable_reg = 0x37000,
1198 .enable_mask = BIT(0),
1212 .halt_reg = 0x38000,
1215 .enable_reg = 0x38000,
1216 .enable_mask = BIT(0),
1230 .halt_reg = 0x39000,
1233 .enable_reg = 0x39000,
1234 .enable_mask = BIT(0),
1248 .halt_reg = 0x45004,
1250 .hwcg_reg = 0x45004,
1253 .enable_reg = 0x45004,
1254 .enable_mask = BIT(0),
1266 .enable_reg = 0x52008,
1282 .enable_reg = 0x52008,
1296 .halt_reg = 0x4500c,
1298 .hwcg_reg = 0x4500c,
1301 .enable_reg = 0x4500c,
1302 .enable_mask = BIT(0),
1311 .halt_reg = 0x45014,
1313 .hwcg_reg = 0x45014,
1316 .enable_reg = 0x45014,
1317 .enable_mask = BIT(0),
1326 .halt_reg = 0x4c008,
1328 .hwcg_reg = 0x4c008,
1331 .enable_reg = 0x4c008,
1332 .enable_mask = BIT(0),
1341 .halt_reg = 0x4d004,
1343 .hwcg_reg = 0x4d004,
1346 .enable_reg = 0x4d004,
1347 .enable_mask = BIT(0),
1356 .halt_reg = 0x4d008,
1359 .enable_reg = 0x4d008,
1360 .enable_mask = BIT(0),
1369 .halt_reg = 0x4d00c,
1372 .enable_reg = 0x4d00c,
1373 .enable_mask = BIT(0),
1382 .halt_reg = 0x4c004,
1384 .hwcg_reg = 0x4c004,
1387 .enable_reg = 0x4c004,
1388 .enable_mask = BIT(0),
1398 .halt_reg = 0x4c140,
1400 .hwcg_reg = 0x4c140,
1403 .enable_reg = 0x4c140,
1404 .enable_mask = BIT(0),
1415 .enable_reg = 0x52008,
1431 .enable_reg = 0x52008,
1445 .halt_reg = 0x2300c,
1448 .enable_reg = 0x2300c,
1449 .enable_mask = BIT(0),
1463 .halt_reg = 0x23004,
1465 .hwcg_reg = 0x23004,
1468 .enable_reg = 0x23004,
1469 .enable_mask = BIT(0),
1478 .halt_reg = 0x23008,
1481 .enable_reg = 0x23008,
1482 .enable_mask = BIT(0),
1491 .halt_reg = 0x24004,
1493 .hwcg_reg = 0x24004,
1496 .enable_reg = 0x52000,
1506 .halt_reg = 0x21014,
1509 .enable_reg = 0x52000,
1519 .halt_reg = 0x2100c,
1522 .enable_reg = 0x52000,
1532 .halt_reg = 0x21144,
1535 .enable_reg = 0x52000,
1550 .halt_reg = 0x21274,
1553 .enable_reg = 0x52000,
1568 .halt_reg = 0x213a4,
1571 .enable_reg = 0x52000,
1586 .halt_reg = 0x214d4,
1589 .enable_reg = 0x52000,
1604 .halt_reg = 0x21604,
1607 .enable_reg = 0x52000,
1622 .halt_reg = 0x21734,
1625 .enable_reg = 0x52000,
1640 .halt_reg = 0x22004,
1643 .enable_reg = 0x52000,
1653 .halt_reg = 0x22008,
1656 .enable_reg = 0x52000,
1666 .halt_reg = 0x22014,
1669 .enable_reg = 0x52000,
1684 .halt_reg = 0x22144,
1687 .enable_reg = 0x52000,
1702 .halt_reg = 0x22274,
1705 .enable_reg = 0x52000,
1720 .halt_reg = 0x223a4,
1723 .enable_reg = 0x52000,
1738 .halt_reg = 0x224d4,
1741 .enable_reg = 0x52000,
1756 .halt_reg = 0x22604,
1759 .enable_reg = 0x52000,
1774 .halt_reg = 0x21004,
1776 .hwcg_reg = 0x21004,
1779 .enable_reg = 0x52000,
1789 .halt_reg = 0x21008,
1791 .hwcg_reg = 0x21008,
1794 .enable_reg = 0x52000,
1804 .halt_reg = 0x2200c,
1806 .hwcg_reg = 0x2200c,
1809 .enable_reg = 0x52000,
1819 .halt_reg = 0x22010,
1821 .hwcg_reg = 0x22010,
1824 .enable_reg = 0x52000,
1834 .halt_reg = 0x4b004,
1837 .enable_reg = 0x4b004,
1838 .enable_mask = BIT(0),
1847 .halt_reg = 0x4b008,
1850 .enable_reg = 0x4b008,
1851 .enable_mask = BIT(0),
1865 .halt_reg = 0x4b03c,
1867 .hwcg_reg = 0x4b03c,
1870 .enable_reg = 0x4b03c,
1871 .enable_mask = BIT(0),
1885 .halt_reg = 0x20008,
1888 .enable_reg = 0x20008,
1889 .enable_mask = BIT(0),
1898 .halt_reg = 0x20004,
1901 .enable_reg = 0x20004,
1902 .enable_mask = BIT(0),
1916 .halt_reg = 0x10140,
1918 .hwcg_reg = 0x10140,
1921 .enable_reg = 0x52000,
1922 .enable_mask = BIT(0),
1936 .halt_reg = 0x8c000,
1939 .enable_reg = 0x8c000,
1940 .enable_mask = BIT(0),
1949 .halt_reg = 0x3a00c,
1951 .hwcg_reg = 0x3a00c,
1954 .enable_reg = 0x3a00c,
1955 .enable_mask = BIT(0),
1964 .halt_reg = 0x3a034,
1966 .hwcg_reg = 0x3a034,
1969 .enable_reg = 0x3a034,
1970 .enable_mask = BIT(0),
1984 .halt_reg = 0x3a0a4,
1986 .hwcg_reg = 0x3a0a4,
1989 .enable_reg = 0x3a0a4,
1990 .enable_mask = BIT(0),
2004 .halt_reg = 0x3a0a4,
2006 .hwcg_reg = 0x3a0a4,
2009 .enable_reg = 0x3a0a4,
2024 .halt_reg = 0x3a0ac,
2026 .hwcg_reg = 0x3a0ac,
2029 .enable_reg = 0x3a0ac,
2030 .enable_mask = BIT(0),
2044 .halt_reg = 0x3a0ac,
2046 .hwcg_reg = 0x3a0ac,
2049 .enable_reg = 0x3a0ac,
2064 .halt_reg = 0x3a014,
2067 .enable_reg = 0x3a014,
2068 .enable_mask = BIT(0),
2077 .halt_reg = 0x3a018,
2080 .enable_reg = 0x3a018,
2081 .enable_mask = BIT(0),
2090 .halt_reg = 0x3a010,
2093 .enable_reg = 0x3a010,
2094 .enable_mask = BIT(0),
2103 .halt_reg = 0x3a09c,
2105 .hwcg_reg = 0x3a09c,
2108 .enable_reg = 0x3a09c,
2109 .enable_mask = BIT(0),
2123 .halt_reg = 0x3a09c,
2125 .hwcg_reg = 0x3a09c,
2128 .enable_reg = 0x3a09c,
2143 .halt_reg = 0x1a00c,
2146 .enable_reg = 0x1a00c,
2147 .enable_mask = BIT(0),
2161 .halt_reg = 0x1a018,
2164 .enable_reg = 0x1a018,
2165 .enable_mask = BIT(0),
2179 .halt_reg = 0x1a014,
2182 .enable_reg = 0x1a014,
2183 .enable_mask = BIT(0),
2192 .halt_reg = 0x8c010,
2195 .enable_reg = 0x8c010,
2196 .enable_mask = BIT(0),
2205 .halt_reg = 0x1a050,
2208 .enable_reg = 0x1a050,
2209 .enable_mask = BIT(0),
2223 .halt_reg = 0x1a054,
2226 .enable_reg = 0x1a054,
2227 .enable_mask = BIT(0),
2241 .halt_reg = 0x1a058,
2243 .hwcg_reg = 0x1a058,
2246 .enable_reg = 0x1a058,
2247 .enable_mask = BIT(0),
2256 .halt_reg = 0x17004,
2258 .hwcg_reg = 0x17004,
2261 .enable_reg = 0x17004,
2262 .enable_mask = BIT(0),
2272 .halt_reg = 0x17014,
2274 .hwcg_reg = 0x17014,
2277 .enable_reg = 0x17014,
2278 .enable_mask = BIT(0),
2287 .halt_reg = 0x17020,
2289 .hwcg_reg = 0x17020,
2292 .enable_reg = 0x17020,
2293 .enable_mask = BIT(0),
2302 .halt_reg = 0x1702c,
2305 .enable_reg = 0x1702c,
2306 .enable_mask = BIT(0),
2316 .gdscr = 0x1a004,
2324 .gdscr = 0x3a004,
2332 .gdscr = 0xb7040,
2341 .gdscr = 0xb7044,
2495 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1d000 },
2496 [GCC_QUSB2PHY_SEC_BCR] = { 0x1e000 },
2497 [GCC_SDCC1_BCR] = { 0x4b000 },
2498 [GCC_SDCC2_BCR] = { 0x20000 },
2499 [GCC_UFS_PHY_BCR] = { 0x3a000 },
2500 [GCC_USB30_PRIM_BCR] = { 0x1a000 },
2501 [GCC_USB3_PHY_PRIM_BCR] = { 0x1c000 },
2502 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1c008 },
2524 .max_register = 0xbf030,
2554 regmap_update_bits(regmap, 0x4cf00, 0x3, 0x3); in gcc_sm6350_probe()
2555 regmap_update_bits(regmap, 0x45f00, 0x3, 0x3); in gcc_sm6350_probe()