Lines Matching +full:xo +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
17 #include "clk-regmap.h"
18 #include "clk-pll.h"
19 #include "clk-rcg.h"
20 #include "clk-branch.h"
21 #include "clk-alpha-pll.h"
22 #include "clk-regmap-divider.h"
23 #include "clk-regmap-mux.h"
60 .fw_name = "xo",
61 .name = "xo",
63 .num_parents = 1,
70 .mult = 1,
76 .num_parents = 1,
89 .num_parents = 1,
103 .fw_name = "xo",
104 .name = "xo",
106 .num_parents = 1,
121 .num_parents = 1,
135 .fw_name = "xo",
136 .name = "xo",
138 .num_parents = 1,
153 .num_parents = 1,
168 .fw_name = "xo",
169 .name = "xo",
171 .num_parents = 1,
186 .num_parents = 1,
192 .mult = 1,
198 .num_parents = 1,
213 .fw_name = "xo",
214 .name = "xo",
216 .num_parents = 1,
230 .num_parents = 1,
245 .fw_name = "xo",
246 .name = "xo",
248 .num_parents = 1,
262 .num_parents = 1,
268 F(19200000, P_XO, 1, 0, 0),
275 { .fw_name = "xo", .name = "xo" },
282 { P_GPLL0, 1 },
301 .mult = 1,
302 .div = 1,
307 .num_parents = 1,
317 .enable_mask = BIT(1),
324 .num_parents = 1,
332 F(19200000, P_XO, 1, 0, 0),
352 F(960000, P_XO, 10, 1, 2),
355 F(12500000, P_GPLL0_DIV2, 16, 1, 2),
356 F(16000000, P_GPLL0, 10, 1, 5),
357 F(19200000, P_XO, 1, 0, 0),
358 F(25000000, P_GPLL0, 16, 1, 2),
513 F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
514 F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
515 F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
516 F(16000000, P_GPLL0_DIV2, 5, 1, 5),
517 F(19200000, P_XO, 1, 0, 0),
518 F(24000000, P_GPLL0, 1, 3, 100),
519 F(25000000, P_GPLL0, 16, 1, 2),
520 F(32000000, P_GPLL0, 1, 1, 25),
521 F(40000000, P_GPLL0, 1, 1, 20),
522 F(46400000, P_GPLL0, 1, 29, 500),
523 F(48000000, P_GPLL0, 1, 3, 50),
524 F(51200000, P_GPLL0, 1, 8, 125),
525 F(56000000, P_GPLL0, 1, 7, 100),
526 F(58982400, P_GPLL0, 1, 1152, 15625),
527 F(60000000, P_GPLL0, 1, 3, 40),
528 F(64000000, P_GPLL0, 12.5, 1, 1),
617 { .fw_name = "xo" },
623 { P_GPLL0, 1 },
627 F(19200000, P_XO, 1, 0, 0),
646 F(19200000, P_XO, 1, 0, 0),
650 { .fw_name = "xo", .name = "xo" },
677 { .fw_name = "xo", .name = "xo" },
730 { .fw_name = "xo", .name = "xo" },
756 F(400000, P_XO, 12, 1, 4),
757 F(24000000, P_GPLL2, 12, 1, 4),
758 F(48000000, P_GPLL2, 12, 1, 2),
767 { .fw_name = "xo", .name = "xo" },
775 { P_GPLL0, 1 },
795 F(19200000, P_XO, 1, 0, 0),
801 { .fw_name = "xo", .name = "xo" },
809 { P_GPLL0, 1 },
850 { .fw_name = "xo", .name = "xo" },
858 { P_GPLL0, 1 },
876 F(19200000, P_XO, 1, 0, 0),
895 F(19200000, P_XO, 1, 0, 0),
896 F(20000000, P_GPLL6, 6, 1, 9),
897 F(60000000, P_GPLL6, 6, 1, 3),
902 { .fw_name = "xo", .name = "xo" },
910 { P_GPLL6, 1 },
931 { .fw_name = "xo", .name = "xo" },
999 { .fw_name = "xo", .name = "xo" },
1027 .enable_mask = BIT(1),
1031 .fw_name = "xo",
1032 .name = "xo",
1034 .num_parents = 1,
1042 .mult = 1,
1048 .num_parents = 1,
1055 F(19200000, P_XO, 1, 0, 0),
1066 { .fw_name = "xo", .name = "xo" },
1074 { P_GPLL0, 1 },
1094 .mult = 1,
1095 .div = 1,
1100 .num_parents = 1,
1107 F(19200000, P_XO, 1, 0, 0),
1126 F(19200000, P_XO, 1, 0, 0),
1127 F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
1132 { .fw_name = "xo", .name = "xo" },
1140 { P_BIAS_PLL_NSS_NOC, 1 },
1159 .mult = 1,
1160 .div = 1,
1165 .num_parents = 1,
1172 F(19200000, P_XO, 1, 0, 0),
1173 F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
1178 { .fw_name = "xo", .name = "xo" },
1185 { P_NSS_CRYPTO_PLL, 1 },
1204 F(19200000, P_XO, 1, 0, 0),
1207 F(1497600000, P_UBI32_PLL, 1, 0, 0),
1208 F(1689600000, P_UBI32_PLL, 1, 0, 0),
1213 { .fw_name = "xo", .name = "xo" },
1223 { P_UBI32_PLL, 1 },
1253 .num_parents = 1,
1283 .num_parents = 1,
1291 F(19200000, P_XO, 1, 0, 0),
1297 { .fw_name = "xo", .name = "xo" },
1303 { P_GPLL0_DIV2, 1 },
1320 F(19200000, P_XO, 1, 0, 0),
1326 { .fw_name = "xo", .name = "xo" },
1333 { P_GPLL0, 1 },
1351 F(19200000, P_XO, 1, 0, 0),
1352 F(300000000, P_BIAS_PLL, 1, 0, 0),
1357 { .fw_name = "xo", .name = "xo" },
1367 { P_BIAS_PLL, 1 },
1388 .mult = 1,
1394 .num_parents = 1,
1401 F(19200000, P_XO, 1, 0, 0),
1403 F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1408 { .fw_name = "xo", .name = "xo" },
1417 { P_UNIPHY0_RX, 1 },
1445 .num_parents = 1,
1453 F(19200000, P_XO, 1, 0, 0),
1455 F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1460 { .fw_name = "xo", .name = "xo" },
1469 { P_UNIPHY0_TX, 1 },
1497 .num_parents = 1,
1526 .num_parents = 1,
1555 .num_parents = 1,
1584 .num_parents = 1,
1613 .num_parents = 1,
1642 .num_parents = 1,
1671 .num_parents = 1,
1679 F(19200000, P_XO, 1, 0, 0),
1684 F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1686 F(312500000, P_UNIPHY1_RX, 1, 0, 0),
1691 { .fw_name = "xo", .name = "xo" },
1703 { P_UNIPHY0_RX, 1 },
1733 .num_parents = 1,
1741 F(19200000, P_XO, 1, 0, 0),
1746 F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1748 F(312500000, P_UNIPHY1_TX, 1, 0, 0),
1753 { .fw_name = "xo", .name = "xo" },
1765 { P_UNIPHY0_TX, 1 },
1795 .num_parents = 1,
1803 F(19200000, P_XO, 1, 0, 0),
1807 F(125000000, P_UNIPHY2_RX, 1, 0, 0),
1810 F(312500000, P_UNIPHY2_RX, 1, 0, 0),
1815 { .fw_name = "xo", .name = "xo" },
1824 { P_UNIPHY2_RX, 1 },
1852 .num_parents = 1,
1860 F(19200000, P_XO, 1, 0, 0),
1864 F(125000000, P_UNIPHY2_TX, 1, 0, 0),
1867 F(312500000, P_UNIPHY2_TX, 1, 0, 0),
1872 { .fw_name = "xo", .name = "xo" },
1881 { P_UNIPHY2_TX, 1 },
1909 .num_parents = 1,
1938 F(19200000, P_XO, 1, 0, 0),
1943 { .fw_name = "xo", .name = "xo" },
1952 { P_GPLL0, 1 },
2009 .num_parents = 1,
2025 .num_parents = 1,
2041 .num_parents = 1,
2057 .num_parents = 1,
2073 .num_parents = 1,
2089 .num_parents = 1,
2105 .num_parents = 1,
2121 .num_parents = 1,
2137 .num_parents = 1,
2153 .num_parents = 1,
2169 .num_parents = 1,
2185 .num_parents = 1,
2201 .num_parents = 1,
2217 .num_parents = 1,
2233 .num_parents = 1,
2249 .num_parents = 1,
2265 .num_parents = 1,
2281 .num_parents = 1,
2297 .num_parents = 1,
2314 .num_parents = 1,
2330 .num_parents = 1,
2346 .num_parents = 1,
2362 .num_parents = 1,
2378 .num_parents = 1,
2394 .num_parents = 1,
2410 .num_parents = 1,
2427 .num_parents = 1,
2443 .num_parents = 1,
2459 .num_parents = 1,
2475 .num_parents = 1,
2491 .num_parents = 1,
2507 .num_parents = 1,
2524 .num_parents = 1,
2540 .num_parents = 1,
2556 .num_parents = 1,
2572 .num_parents = 1,
2588 .num_parents = 1,
2604 .num_parents = 1,
2620 .num_parents = 1,
2637 .num_parents = 1,
2653 .num_parents = 1,
2669 .num_parents = 1,
2685 .num_parents = 1,
2701 .num_parents = 1,
2717 .num_parents = 1,
2733 .num_parents = 1,
2750 .num_parents = 1,
2766 .num_parents = 1,
2782 .num_parents = 1,
2798 .num_parents = 1,
2814 .num_parents = 1,
2830 .num_parents = 1,
2846 .num_parents = 1,
2862 .num_parents = 1,
2878 .num_parents = 1,
2894 .num_parents = 1,
2910 .num_parents = 1,
2926 .num_parents = 1,
2942 .num_parents = 1,
2958 .num_parents = 1,
2974 .num_parents = 1,
2990 .num_parents = 1,
3006 .num_parents = 1,
3022 .num_parents = 1,
3038 .num_parents = 1,
3054 .num_parents = 1,
3070 .num_parents = 1,
3086 .num_parents = 1,
3103 .num_parents = 1,
3119 .num_parents = 1,
3135 .num_parents = 1,
3151 .num_parents = 1,
3167 .num_parents = 1,
3183 .num_parents = 1,
3199 .num_parents = 1,
3215 .num_parents = 1,
3231 .num_parents = 1,
3247 .num_parents = 1,
3263 .num_parents = 1,
3280 .num_parents = 1,
3297 .num_parents = 1,
3314 .num_parents = 1,
3331 .num_parents = 1,
3348 .num_parents = 1,
3365 .num_parents = 1,
3382 .num_parents = 1,
3399 .num_parents = 1,
3416 .num_parents = 1,
3433 .num_parents = 1,
3449 .num_parents = 1,
3465 .num_parents = 1,
3481 .num_parents = 1,
3497 .num_parents = 1,
3513 .num_parents = 1,
3529 .num_parents = 1,
3545 .num_parents = 1,
3561 .num_parents = 1,
3577 .num_parents = 1,
3593 .num_parents = 1,
3609 .num_parents = 1,
3625 .num_parents = 1,
3641 .num_parents = 1,
3657 .num_parents = 1,
3673 .num_parents = 1,
3689 .num_parents = 1,
3705 .num_parents = 1,
3721 .num_parents = 1,
3737 .num_parents = 1,
3753 .num_parents = 1,
3769 .num_parents = 1,
3785 .num_parents = 1,
3801 .num_parents = 1,
3817 .num_parents = 1,
3833 .num_parents = 1,
3849 .num_parents = 1,
3865 .num_parents = 1,
3881 .num_parents = 1,
3897 .num_parents = 1,
3913 .num_parents = 1,
3929 .num_parents = 1,
3945 .num_parents = 1,
3961 .num_parents = 1,
3977 .num_parents = 1,
3993 .num_parents = 1,
4009 .num_parents = 1,
4025 .num_parents = 1,
4041 .num_parents = 1,
4057 .num_parents = 1,
4073 .num_parents = 1,
4089 .num_parents = 1,
4106 .num_parents = 1,
4118 .enable_mask = BIT(1),
4123 .num_parents = 1,
4140 .num_parents = 1,
4156 .num_parents = 1,
4172 .num_parents = 1,
4188 .num_parents = 1,
4196 F(19200000, P_XO, 1, 0, 0),
4219 .enable_mask = BIT(1),
4225 .num_parents = 1,
4243 .num_parents = 1,
4271 .aux_output_mask = BIT(1),
4625 [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4653 [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4661 [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
4668 [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = GENMASK(13, 4) | BIT(1) },
4670 [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = GENMASK(5, 4) | BIT(1) },
4672 [GCC_UNIPHY2_SOFT_RESET] = { .reg = 0x56204, .bitmask = GENMASK(5, 4) | BIT(1) },
4675 [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = BIT(24) | GENMASK(1, 0) },
4689 { .compatible = "qcom,gcc-ipq8074" },
4735 .name = "qcom,gcc-ipq8074",
4754 MODULE_ALIAS("platform:gcc-ipq8074");