Lines Matching +full:0 +full:x29000
52 .offset = 0x21000,
55 .enable_reg = 0x0b000,
56 .enable_mask = BIT(0),
82 .offset = 0x21000,
95 .offset = 0x4a000,
98 .enable_reg = 0x0b000,
114 .offset = 0x4a000,
127 .offset = 0x24000,
130 .enable_reg = 0x0b000,
146 .offset = 0x24000,
159 .offset = 0x37000,
163 .enable_reg = 0x0b000,
179 .offset = 0x37000,
204 .offset = 0x25000,
208 .enable_reg = 0x0b000,
223 .offset = 0x25000,
237 .offset = 0x22000,
240 .enable_reg = 0x0b000,
255 .offset = 0x22000,
268 F(19200000, P_XO, 1, 0, 0),
269 F(50000000, P_GPLL0, 16, 0, 0),
270 F(100000000, P_GPLL0, 8, 0, 0),
281 { P_XO, 0 },
287 .cmd_rcgr = 0x27000,
314 .halt_reg = 0x30000,
316 .enable_reg = 0x30000,
332 F(19200000, P_XO, 1, 0, 0),
333 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
334 F(50000000, P_GPLL0, 16, 0, 0),
339 .cmd_rcgr = 0x0200c,
353 F(4800000, P_XO, 4, 0, 0),
354 F(9600000, P_XO, 2, 0, 0),
357 F(19200000, P_XO, 1, 0, 0),
359 F(50000000, P_GPLL0, 16, 0, 0),
364 .cmd_rcgr = 0x02024,
378 .cmd_rcgr = 0x03000,
391 .cmd_rcgr = 0x03014,
405 .cmd_rcgr = 0x04000,
418 .cmd_rcgr = 0x04014,
432 .cmd_rcgr = 0x05000,
445 .cmd_rcgr = 0x05014,
459 .cmd_rcgr = 0x06000,
472 .cmd_rcgr = 0x06014,
486 .cmd_rcgr = 0x07000,
499 .cmd_rcgr = 0x07014,
517 F(19200000, P_XO, 1, 0, 0),
533 .cmd_rcgr = 0x02044,
547 .cmd_rcgr = 0x03034,
561 .cmd_rcgr = 0x04034,
575 .cmd_rcgr = 0x05034,
589 .cmd_rcgr = 0x06034,
603 .cmd_rcgr = 0x07034,
622 { P_XO, 0 },
627 F(19200000, P_XO, 1, 0, 0),
628 F(200000000, P_GPLL0, 4, 0, 0),
633 .cmd_rcgr = 0x75054,
646 F(19200000, P_XO, 1, 0, 0),
656 { P_XO, 0 },
662 .cmd_rcgr = 0x75024,
681 { P_PCIE20_PHY0_PIPE, 0 },
686 .reg = 0x7501c,
702 .cmd_rcgr = 0x76054,
715 .cmd_rcgr = 0x76024,
734 { P_PCIE20_PHY1_PIPE, 0 },
739 .reg = 0x7601c,
759 F(96000000, P_GPLL2, 12, 0, 0),
760 F(177777778, P_GPLL0, 4.5, 0, 0),
761 F(192000000, P_GPLL2, 6, 0, 0),
762 F(384000000, P_GPLL2, 3, 0, 0),
774 { P_XO, 0 },
781 .cmd_rcgr = 0x42004,
795 F(19200000, P_XO, 1, 0, 0),
796 F(160000000, P_GPLL0, 5, 0, 0),
797 F(308570000, P_GPLL6, 3.5, 0, 0),
808 { P_XO, 0 },
815 .cmd_rcgr = 0x5d000,
829 .cmd_rcgr = 0x43004,
843 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
844 F(100000000, P_GPLL0, 8, 0, 0),
845 F(133330000, P_GPLL0, 6, 0, 0),
856 { P_XO, 0 },
862 .cmd_rcgr = 0x3e00c,
876 F(19200000, P_XO, 1, 0, 0),
881 .cmd_rcgr = 0x3e05c,
895 F(19200000, P_XO, 1, 0, 0),
909 { P_XO, 0 },
916 .cmd_rcgr = 0x3e020,
935 { P_USB3PHY_0_PIPE, 0 },
940 .reg = 0x3e048,
956 .cmd_rcgr = 0x3f00c,
970 .cmd_rcgr = 0x3f05c,
984 .cmd_rcgr = 0x3f020,
1003 { P_USB3PHY_1_PIPE, 0 },
1008 .reg = 0x3f048,
1024 .halt_reg = 0x30018,
1026 .enable_reg = 0x30018,
1055 F(19200000, P_XO, 1, 0, 0),
1056 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1057 F(100000000, P_GPLL0, 8, 0, 0),
1058 F(133333333, P_GPLL0, 6, 0, 0),
1059 F(160000000, P_GPLL0, 5, 0, 0),
1060 F(200000000, P_GPLL0, 4, 0, 0),
1061 F(266666667, P_GPLL0, 3, 0, 0),
1073 { P_XO, 0 },
1080 .cmd_rcgr = 0x26004,
1107 F(19200000, P_XO, 1, 0, 0),
1108 F(200000000, P_GPLL0, 4, 0, 0),
1113 .cmd_rcgr = 0x68098,
1126 F(19200000, P_XO, 1, 0, 0),
1127 F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
1139 { P_XO, 0 },
1146 .cmd_rcgr = 0x68088,
1172 F(19200000, P_XO, 1, 0, 0),
1173 F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
1184 { P_XO, 0 },
1190 .cmd_rcgr = 0x68144,
1204 F(19200000, P_XO, 1, 0, 0),
1205 F(187200000, P_UBI32_PLL, 8, 0, 0),
1206 F(748800000, P_UBI32_PLL, 2, 0, 0),
1207 F(1497600000, P_UBI32_PLL, 1, 0, 0),
1208 F(1689600000, P_UBI32_PLL, 1, 0, 0),
1222 { P_XO, 0 },
1231 .cmd_rcgr = 0x68104,
1245 .reg = 0x68118,
1246 .shift = 0,
1261 .cmd_rcgr = 0x68124,
1275 .reg = 0x68138,
1276 .shift = 0,
1291 F(19200000, P_XO, 1, 0, 0),
1292 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1302 { P_XO, 0 },
1307 .cmd_rcgr = 0x68090,
1320 F(19200000, P_XO, 1, 0, 0),
1321 F(400000000, P_GPLL0, 2, 0, 0),
1332 { P_XO, 0 },
1338 .cmd_rcgr = 0x68158,
1351 F(19200000, P_XO, 1, 0, 0),
1352 F(300000000, P_BIAS_PLL, 1, 0, 0),
1366 { P_XO, 0 },
1375 .cmd_rcgr = 0x68080,
1401 F(19200000, P_XO, 1, 0, 0),
1402 F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1403 F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1416 { P_XO, 0 },
1424 .cmd_rcgr = 0x68020,
1437 .reg = 0x68400,
1438 .shift = 0,
1453 F(19200000, P_XO, 1, 0, 0),
1454 F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1455 F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1468 { P_XO, 0 },
1476 .cmd_rcgr = 0x68028,
1489 .reg = 0x68404,
1490 .shift = 0,
1505 .cmd_rcgr = 0x68030,
1518 .reg = 0x68410,
1519 .shift = 0,
1534 .cmd_rcgr = 0x68038,
1547 .reg = 0x68414,
1548 .shift = 0,
1563 .cmd_rcgr = 0x68040,
1576 .reg = 0x68420,
1577 .shift = 0,
1592 .cmd_rcgr = 0x68048,
1605 .reg = 0x68424,
1606 .shift = 0,
1621 .cmd_rcgr = 0x68050,
1634 .reg = 0x68430,
1635 .shift = 0,
1650 .cmd_rcgr = 0x68058,
1663 .reg = 0x68434,
1664 .shift = 0,
1679 F(19200000, P_XO, 1, 0, 0),
1680 F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
1681 F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1682 F(78125000, P_UNIPHY1_RX, 4, 0, 0),
1683 F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
1684 F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1685 F(156250000, P_UNIPHY1_RX, 2, 0, 0),
1686 F(312500000, P_UNIPHY1_RX, 1, 0, 0),
1702 { P_XO, 0 },
1712 .cmd_rcgr = 0x68060,
1725 .reg = 0x68440,
1726 .shift = 0,
1741 F(19200000, P_XO, 1, 0, 0),
1742 F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
1743 F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1744 F(78125000, P_UNIPHY1_TX, 4, 0, 0),
1745 F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
1746 F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1747 F(156250000, P_UNIPHY1_TX, 2, 0, 0),
1748 F(312500000, P_UNIPHY1_TX, 1, 0, 0),
1764 { P_XO, 0 },
1774 .cmd_rcgr = 0x68068,
1787 .reg = 0x68444,
1788 .shift = 0,
1803 F(19200000, P_XO, 1, 0, 0),
1804 F(25000000, P_UNIPHY2_RX, 5, 0, 0),
1805 F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
1806 F(78125000, P_UNIPHY2_RX, 4, 0, 0),
1807 F(125000000, P_UNIPHY2_RX, 1, 0, 0),
1808 F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
1809 F(156250000, P_UNIPHY2_RX, 2, 0, 0),
1810 F(312500000, P_UNIPHY2_RX, 1, 0, 0),
1823 { P_XO, 0 },
1831 .cmd_rcgr = 0x68070,
1844 .reg = 0x68450,
1845 .shift = 0,
1860 F(19200000, P_XO, 1, 0, 0),
1861 F(25000000, P_UNIPHY2_TX, 5, 0, 0),
1862 F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
1863 F(78125000, P_UNIPHY2_TX, 4, 0, 0),
1864 F(125000000, P_UNIPHY2_TX, 1, 0, 0),
1865 F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
1866 F(156250000, P_UNIPHY2_TX, 2, 0, 0),
1867 F(312500000, P_UNIPHY2_TX, 1, 0, 0),
1880 { P_XO, 0 },
1888 .cmd_rcgr = 0x68078,
1901 .reg = 0x68454,
1902 .shift = 0,
1917 F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1918 F(80000000, P_GPLL0, 10, 0, 0),
1919 F(100000000, P_GPLL0, 8, 0, 0),
1920 F(160000000, P_GPLL0, 5, 0, 0),
1925 .cmd_rcgr = 0x16004,
1938 F(19200000, P_XO, 1, 0, 0),
1951 { P_XO, 0 },
1959 .cmd_rcgr = 0x08004,
1973 .cmd_rcgr = 0x09004,
1987 .cmd_rcgr = 0x0a004,
2001 .halt_reg = 0x01008,
2003 .enable_reg = 0x01008,
2004 .enable_mask = BIT(0),
2017 .halt_reg = 0x02008,
2019 .enable_reg = 0x02008,
2020 .enable_mask = BIT(0),
2033 .halt_reg = 0x02004,
2035 .enable_reg = 0x02004,
2036 .enable_mask = BIT(0),
2049 .halt_reg = 0x03010,
2051 .enable_reg = 0x03010,
2052 .enable_mask = BIT(0),
2065 .halt_reg = 0x0300c,
2067 .enable_reg = 0x0300c,
2068 .enable_mask = BIT(0),
2081 .halt_reg = 0x04010,
2083 .enable_reg = 0x04010,
2084 .enable_mask = BIT(0),
2097 .halt_reg = 0x0400c,
2099 .enable_reg = 0x0400c,
2100 .enable_mask = BIT(0),
2113 .halt_reg = 0x05010,
2115 .enable_reg = 0x05010,
2116 .enable_mask = BIT(0),
2129 .halt_reg = 0x0500c,
2131 .enable_reg = 0x0500c,
2132 .enable_mask = BIT(0),
2145 .halt_reg = 0x06010,
2147 .enable_reg = 0x06010,
2148 .enable_mask = BIT(0),
2161 .halt_reg = 0x0600c,
2163 .enable_reg = 0x0600c,
2164 .enable_mask = BIT(0),
2177 .halt_reg = 0x07010,
2179 .enable_reg = 0x07010,
2180 .enable_mask = BIT(0),
2193 .halt_reg = 0x0700c,
2195 .enable_reg = 0x0700c,
2196 .enable_mask = BIT(0),
2209 .halt_reg = 0x0203c,
2211 .enable_reg = 0x0203c,
2212 .enable_mask = BIT(0),
2225 .halt_reg = 0x0302c,
2227 .enable_reg = 0x0302c,
2228 .enable_mask = BIT(0),
2241 .halt_reg = 0x0402c,
2243 .enable_reg = 0x0402c,
2244 .enable_mask = BIT(0),
2257 .halt_reg = 0x0502c,
2259 .enable_reg = 0x0502c,
2260 .enable_mask = BIT(0),
2273 .halt_reg = 0x0602c,
2275 .enable_reg = 0x0602c,
2276 .enable_mask = BIT(0),
2289 .halt_reg = 0x0702c,
2291 .enable_reg = 0x0702c,
2292 .enable_mask = BIT(0),
2305 .halt_reg = 0x13004,
2308 .enable_reg = 0x0b004,
2322 .halt_reg = 0x57024,
2324 .enable_reg = 0x57024,
2325 .enable_mask = BIT(0),
2338 .halt_reg = 0x57020,
2340 .enable_reg = 0x57020,
2341 .enable_mask = BIT(0),
2354 .halt_reg = 0x75010,
2356 .enable_reg = 0x75010,
2357 .enable_mask = BIT(0),
2370 .halt_reg = 0x75014,
2372 .enable_reg = 0x75014,
2373 .enable_mask = BIT(0),
2386 .halt_reg = 0x75008,
2388 .enable_reg = 0x75008,
2389 .enable_mask = BIT(0),
2402 .halt_reg = 0x7500c,
2404 .enable_reg = 0x7500c,
2405 .enable_mask = BIT(0),
2418 .halt_reg = 0x75018,
2421 .enable_reg = 0x75018,
2422 .enable_mask = BIT(0),
2435 .halt_reg = 0x26048,
2437 .enable_reg = 0x26048,
2438 .enable_mask = BIT(0),
2451 .halt_reg = 0x76010,
2453 .enable_reg = 0x76010,
2454 .enable_mask = BIT(0),
2467 .halt_reg = 0x76014,
2469 .enable_reg = 0x76014,
2470 .enable_mask = BIT(0),
2483 .halt_reg = 0x76008,
2485 .enable_reg = 0x76008,
2486 .enable_mask = BIT(0),
2499 .halt_reg = 0x7600c,
2501 .enable_reg = 0x7600c,
2502 .enable_mask = BIT(0),
2515 .halt_reg = 0x76018,
2518 .enable_reg = 0x76018,
2519 .enable_mask = BIT(0),
2532 .halt_reg = 0x2604c,
2534 .enable_reg = 0x2604c,
2535 .enable_mask = BIT(0),
2548 .halt_reg = 0x3e044,
2550 .enable_reg = 0x3e044,
2551 .enable_mask = BIT(0),
2564 .halt_reg = 0x26040,
2566 .enable_reg = 0x26040,
2567 .enable_mask = BIT(0),
2580 .halt_reg = 0x3e000,
2582 .enable_reg = 0x3e000,
2583 .enable_mask = BIT(0),
2596 .halt_reg = 0x3e008,
2598 .enable_reg = 0x3e008,
2599 .enable_mask = BIT(0),
2612 .halt_reg = 0x3e080,
2614 .enable_reg = 0x3e080,
2615 .enable_mask = BIT(0),
2628 .halt_reg = 0x3e040,
2631 .enable_reg = 0x3e040,
2632 .enable_mask = BIT(0),
2645 .halt_reg = 0x3e004,
2647 .enable_reg = 0x3e004,
2648 .enable_mask = BIT(0),
2661 .halt_reg = 0x3f044,
2663 .enable_reg = 0x3f044,
2664 .enable_mask = BIT(0),
2677 .halt_reg = 0x26044,
2679 .enable_reg = 0x26044,
2680 .enable_mask = BIT(0),
2693 .halt_reg = 0x3f000,
2695 .enable_reg = 0x3f000,
2696 .enable_mask = BIT(0),
2709 .halt_reg = 0x3f008,
2711 .enable_reg = 0x3f008,
2712 .enable_mask = BIT(0),
2725 .halt_reg = 0x3f080,
2727 .enable_reg = 0x3f080,
2728 .enable_mask = BIT(0),
2741 .halt_reg = 0x3f040,
2744 .enable_reg = 0x3f040,
2745 .enable_mask = BIT(0),
2758 .halt_reg = 0x3f004,
2760 .enable_reg = 0x3f004,
2761 .enable_mask = BIT(0),
2774 .halt_reg = 0x4201c,
2776 .enable_reg = 0x4201c,
2777 .enable_mask = BIT(0),
2790 .halt_reg = 0x42018,
2792 .enable_reg = 0x42018,
2793 .enable_mask = BIT(0),
2806 .halt_reg = 0x5d014,
2808 .enable_reg = 0x5d014,
2809 .enable_mask = BIT(0),
2822 .halt_reg = 0x4301c,
2824 .enable_reg = 0x4301c,
2825 .enable_mask = BIT(0),
2838 .halt_reg = 0x43018,
2840 .enable_reg = 0x43018,
2841 .enable_mask = BIT(0),
2854 .halt_reg = 0x1d03c,
2856 .enable_reg = 0x1d03c,
2857 .enable_mask = BIT(0),
2870 .halt_reg = 0x68174,
2872 .enable_reg = 0x68174,
2873 .enable_mask = BIT(0),
2886 .halt_reg = 0x68170,
2888 .enable_reg = 0x68170,
2889 .enable_mask = BIT(0),
2902 .halt_reg = 0x68160,
2904 .enable_reg = 0x68160,
2905 .enable_mask = BIT(0),
2918 .halt_reg = 0x68164,
2920 .enable_reg = 0x68164,
2921 .enable_mask = BIT(0),
2934 .halt_reg = 0x68318,
2936 .enable_reg = 0x68318,
2937 .enable_mask = BIT(0),
2950 .halt_reg = 0x6819c,
2952 .enable_reg = 0x6819c,
2953 .enable_mask = BIT(0),
2966 .halt_reg = 0x68198,
2968 .enable_reg = 0x68198,
2969 .enable_mask = BIT(0),
2982 .halt_reg = 0x68178,
2984 .enable_reg = 0x68178,
2985 .enable_mask = BIT(0),
2998 .halt_reg = 0x68168,
3000 .enable_reg = 0x68168,
3001 .enable_mask = BIT(0),
3014 .halt_reg = 0x6833c,
3016 .enable_reg = 0x6833c,
3017 .enable_mask = BIT(0),
3030 .halt_reg = 0x68194,
3032 .enable_reg = 0x68194,
3033 .enable_mask = BIT(0),
3046 .halt_reg = 0x68190,
3048 .enable_reg = 0x68190,
3049 .enable_mask = BIT(0),
3062 .halt_reg = 0x68338,
3064 .enable_reg = 0x68338,
3065 .enable_mask = BIT(0),
3078 .halt_reg = 0x6816c,
3080 .enable_reg = 0x6816c,
3081 .enable_mask = BIT(0),
3094 .halt_reg = 0x68310,
3097 .enable_reg = 0x68310,
3098 .enable_mask = BIT(0),
3111 .halt_reg = 0x6830c,
3113 .enable_reg = 0x6830c,
3114 .enable_mask = BIT(0),
3127 .halt_reg = 0x68308,
3129 .enable_reg = 0x68308,
3130 .enable_mask = BIT(0),
3143 .halt_reg = 0x68314,
3145 .enable_reg = 0x68314,
3146 .enable_mask = BIT(0),
3159 .halt_reg = 0x68304,
3161 .enable_reg = 0x68304,
3162 .enable_mask = BIT(0),
3175 .halt_reg = 0x68300,
3177 .enable_reg = 0x68300,
3178 .enable_mask = BIT(0),
3191 .halt_reg = 0x68180,
3193 .enable_reg = 0x68180,
3194 .enable_mask = BIT(0),
3207 .halt_reg = 0x68188,
3209 .enable_reg = 0x68188,
3210 .enable_mask = BIT(0),
3223 .halt_reg = 0x68184,
3225 .enable_reg = 0x68184,
3226 .enable_mask = BIT(0),
3239 .halt_reg = 0x68270,
3241 .enable_reg = 0x68270,
3242 .enable_mask = BIT(0),
3255 .halt_reg = 0x68274,
3257 .enable_reg = 0x68274,
3258 .enable_mask = BIT(0),
3271 .halt_reg = 0x6820c,
3274 .enable_reg = 0x6820c,
3275 .enable_mask = BIT(0),
3288 .halt_reg = 0x68200,
3291 .enable_reg = 0x68200,
3292 .enable_mask = BIT(0),
3305 .halt_reg = 0x68204,
3308 .enable_reg = 0x68204,
3309 .enable_mask = BIT(0),
3322 .halt_reg = 0x68210,
3325 .enable_reg = 0x68210,
3326 .enable_mask = BIT(0),
3339 .halt_reg = 0x68208,
3342 .enable_reg = 0x68208,
3343 .enable_mask = BIT(0),
3356 .halt_reg = 0x6822c,
3359 .enable_reg = 0x6822c,
3360 .enable_mask = BIT(0),
3373 .halt_reg = 0x68220,
3376 .enable_reg = 0x68220,
3377 .enable_mask = BIT(0),
3390 .halt_reg = 0x68224,
3393 .enable_reg = 0x68224,
3394 .enable_mask = BIT(0),
3407 .halt_reg = 0x68230,
3410 .enable_reg = 0x68230,
3411 .enable_mask = BIT(0),
3424 .halt_reg = 0x68228,
3427 .enable_reg = 0x68228,
3428 .enable_mask = BIT(0),
3441 .halt_reg = 0x56308,
3443 .enable_reg = 0x56308,
3444 .enable_mask = BIT(0),
3457 .halt_reg = 0x5630c,
3459 .enable_reg = 0x5630c,
3460 .enable_mask = BIT(0),
3473 .halt_reg = 0x58004,
3475 .enable_reg = 0x58004,
3476 .enable_mask = BIT(0),
3489 .halt_reg = 0x56008,
3491 .enable_reg = 0x56008,
3492 .enable_mask = BIT(0),
3505 .halt_reg = 0x5600c,
3507 .enable_reg = 0x5600c,
3508 .enable_mask = BIT(0),
3521 .halt_reg = 0x56108,
3523 .enable_reg = 0x56108,
3524 .enable_mask = BIT(0),
3537 .halt_reg = 0x5610c,
3539 .enable_reg = 0x5610c,
3540 .enable_mask = BIT(0),
3553 .halt_reg = 0x56208,
3555 .enable_reg = 0x56208,
3556 .enable_mask = BIT(0),
3569 .halt_reg = 0x5620c,
3571 .enable_reg = 0x5620c,
3572 .enable_mask = BIT(0),
3585 .halt_reg = 0x68240,
3587 .enable_reg = 0x68240,
3588 .enable_mask = BIT(0),
3601 .halt_reg = 0x68244,
3603 .enable_reg = 0x68244,
3604 .enable_mask = BIT(0),
3617 .halt_reg = 0x68248,
3619 .enable_reg = 0x68248,
3620 .enable_mask = BIT(0),
3633 .halt_reg = 0x6824c,
3635 .enable_reg = 0x6824c,
3636 .enable_mask = BIT(0),
3649 .halt_reg = 0x68250,
3651 .enable_reg = 0x68250,
3652 .enable_mask = BIT(0),
3665 .halt_reg = 0x68254,
3667 .enable_reg = 0x68254,
3668 .enable_mask = BIT(0),
3681 .halt_reg = 0x68258,
3683 .enable_reg = 0x68258,
3684 .enable_mask = BIT(0),
3697 .halt_reg = 0x6825c,
3699 .enable_reg = 0x6825c,
3700 .enable_mask = BIT(0),
3713 .halt_reg = 0x68260,
3715 .enable_reg = 0x68260,
3716 .enable_mask = BIT(0),
3729 .halt_reg = 0x68264,
3731 .enable_reg = 0x68264,
3732 .enable_mask = BIT(0),
3745 .halt_reg = 0x68268,
3747 .enable_reg = 0x68268,
3748 .enable_mask = BIT(0),
3761 .halt_reg = 0x6826c,
3763 .enable_reg = 0x6826c,
3764 .enable_mask = BIT(0),
3777 .halt_reg = 0x68320,
3779 .enable_reg = 0x68320,
3780 .enable_mask = BIT(0),
3793 .halt_reg = 0x68324,
3795 .enable_reg = 0x68324,
3796 .enable_mask = BIT(0),
3809 .halt_reg = 0x68328,
3811 .enable_reg = 0x68328,
3812 .enable_mask = BIT(0),
3825 .halt_reg = 0x6832c,
3827 .enable_reg = 0x6832c,
3828 .enable_mask = BIT(0),
3841 .halt_reg = 0x68330,
3843 .enable_reg = 0x68330,
3844 .enable_mask = BIT(0),
3857 .halt_reg = 0x68334,
3859 .enable_reg = 0x68334,
3860 .enable_mask = BIT(0),
3873 .halt_reg = 0x56010,
3875 .enable_reg = 0x56010,
3876 .enable_mask = BIT(0),
3889 .halt_reg = 0x56014,
3891 .enable_reg = 0x56014,
3892 .enable_mask = BIT(0),
3905 .halt_reg = 0x56018,
3907 .enable_reg = 0x56018,
3908 .enable_mask = BIT(0),
3921 .halt_reg = 0x5601c,
3923 .enable_reg = 0x5601c,
3924 .enable_mask = BIT(0),
3937 .halt_reg = 0x56020,
3939 .enable_reg = 0x56020,
3940 .enable_mask = BIT(0),
3953 .halt_reg = 0x56024,
3955 .enable_reg = 0x56024,
3956 .enable_mask = BIT(0),
3969 .halt_reg = 0x56028,
3971 .enable_reg = 0x56028,
3972 .enable_mask = BIT(0),
3985 .halt_reg = 0x5602c,
3987 .enable_reg = 0x5602c,
3988 .enable_mask = BIT(0),
4001 .halt_reg = 0x56030,
4003 .enable_reg = 0x56030,
4004 .enable_mask = BIT(0),
4017 .halt_reg = 0x56034,
4019 .enable_reg = 0x56034,
4020 .enable_mask = BIT(0),
4033 .halt_reg = 0x56110,
4035 .enable_reg = 0x56110,
4036 .enable_mask = BIT(0),
4049 .halt_reg = 0x56114,
4051 .enable_reg = 0x56114,
4052 .enable_mask = BIT(0),
4065 .halt_reg = 0x56210,
4067 .enable_reg = 0x56210,
4068 .enable_mask = BIT(0),
4081 .halt_reg = 0x56214,
4083 .enable_reg = 0x56214,
4084 .enable_mask = BIT(0),
4097 .halt_reg = 0x16024,
4100 .enable_reg = 0x0b004,
4101 .enable_mask = BIT(0),
4114 .halt_reg = 0x16020,
4117 .enable_reg = 0x0b004,
4131 .halt_reg = 0x1601c,
4134 .enable_reg = 0x0b004,
4148 .halt_reg = 0x08000,
4150 .enable_reg = 0x08000,
4151 .enable_mask = BIT(0),
4164 .halt_reg = 0x09000,
4166 .enable_reg = 0x09000,
4167 .enable_mask = BIT(0),
4180 .halt_reg = 0x0a000,
4182 .enable_reg = 0x0a000,
4183 .enable_mask = BIT(0),
4196 F(19200000, P_XO, 1, 0, 0),
4197 F(100000000, P_GPLL0, 8, 0, 0),
4202 .cmd_rcgr = 0x75070,
4215 .halt_reg = 0x75070,
4218 .enable_reg = 0x75070,
4233 .halt_reg = 0x75048,
4236 .enable_reg = 0x75048,
4237 .enable_mask = BIT(0),
4251 .gdscr = 0x3e078,
4259 .gdscr = 0x3f078,
4267 .l = 0x4e,
4268 .config_ctl_val = 0x200d4aa8,
4269 .config_ctl_hi_val = 0x3c2,
4270 .main_output_mask = BIT(0),
4272 .pre_div_val = 0x0,
4274 .post_div_val = 0x0,
4279 .l = 0x3e,
4280 .alpha = 0x0,
4281 .alpha_hi = 0x80,
4282 .config_ctl_val = 0x4001055b,
4283 .main_output_mask = BIT(0),
4284 .pre_div_val = 0x0,
4286 .post_div_val = 0x1 << 8,
4289 .vco_val = 0x0,
4535 [GCC_BLSP1_BCR] = { 0x01000, 0 },
4536 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4537 [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4538 [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4539 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4540 [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4541 [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4542 [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4543 [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4544 [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4545 [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4546 [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4547 [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4548 [GCC_IMEM_BCR] = { 0x0e000, 0 },
4549 [GCC_SMMU_BCR] = { 0x12000, 0 },
4550 [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4551 [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4552 [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4553 [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4554 [GCC_PRNG_BCR] = { 0x13000, 0 },
4555 [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4556 [GCC_CRYPTO_BCR] = { 0x16000, 0 },
4557 [GCC_WCSS_BCR] = { 0x18000, 0 },
4558 [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4559 [GCC_NSS_BCR] = { 0x19000, 0 },
4560 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4561 [GCC_ADSS_BCR] = { 0x1c000, 0 },
4562 [GCC_DDRSS_BCR] = { 0x1e000, 0 },
4563 [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4564 [GCC_PCNOC_BCR] = { 0x27018, 0 },
4565 [GCC_TCSR_BCR] = { 0x28000, 0 },
4566 [GCC_QDSS_BCR] = { 0x29000, 0 },
4567 [GCC_DCD_BCR] = { 0x2a000, 0 },
4568 [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4569 [GCC_MPM_BCR] = { 0x2c000, 0 },
4570 [GCC_SPMI_BCR] = { 0x2e000, 0 },
4571 [GCC_SPDM_BCR] = { 0x2f000, 0 },
4572 [GCC_RBCPR_BCR] = { 0x33000, 0 },
4573 [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4574 [GCC_TLMM_BCR] = { 0x34000, 0 },
4575 [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4576 [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4577 [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4578 [GCC_USB0_BCR] = { 0x3e070, 0 },
4579 [GCC_USB1_PHY_BCR] = { 0x3f034, 0 },
4580 [GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 },
4581 [GCC_USB1_BCR] = { 0x3f070, 0 },
4582 [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4583 [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4584 [GCC_SDCC1_BCR] = { 0x42000, 0 },
4585 [GCC_SDCC2_BCR] = { 0x43000, 0 },
4586 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4587 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 },
4588 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 },
4589 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4590 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4591 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4592 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4593 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4594 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4595 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4596 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4597 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4598 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4599 [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4600 [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4601 [GCC_UNIPHY2_BCR] = { 0x56200, 0 },
4602 [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4603 [GCC_QPIC_BCR] = { 0x57018, 0 },
4604 [GCC_MDIO_BCR] = { 0x58000, 0 },
4605 [GCC_PCIE1_TBU_BCR] = { 0x65000, 0 },
4606 [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4607 [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4608 [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4609 [GCC_USB1_TBU_BCR] = { 0x6a004, 0 },
4610 [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4611 [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4612 [GCC_PCIE0_BCR] = { 0x75004, 0 },
4613 [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4614 [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4615 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4616 [GCC_PCIE1_BCR] = { 0x76004, 0 },
4617 [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
4618 [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
4619 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
4620 [GCC_DCC_BCR] = { 0x77000, 0 },
4621 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4622 [GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
4623 [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4624 [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4625 [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4626 [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4627 [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4628 [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4629 [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4630 [GCC_UBI1_AXI_ARES] = { 0x68010, 8 },
4631 [GCC_UBI1_AHB_ARES] = { 0x68010, 9 },
4632 [GCC_UBI1_NC_AXI_ARES] = { 0x68010, 10 },
4633 [GCC_UBI1_DBG_ARES] = { 0x68010, 11 },
4634 [GCC_UBI1_CORE_CLAMP_ENABLE] = { 0x68010, 12 },
4635 [GCC_UBI1_CLKRST_CLAMP_ENABLE] = { 0x68010, 13 },
4636 [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4637 [GCC_NSS_IMEM_ARES] = { 0x68010, 17 },
4638 [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4639 [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4640 [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4641 [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4642 [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4643 [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4644 [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4645 [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4646 [GCC_NSSNOC_UBI1_AHB_ARES] = { 0x68010, 26 },
4647 [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4648 [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4649 [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4650 [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4651 [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4652 [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4653 [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4654 [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4655 [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4656 [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4657 [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4658 [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4659 [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
4660 [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
4661 [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
4662 [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
4663 [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
4664 [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
4665 [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
4666 [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
4667 [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = GENMASK(19, 16) },
4668 [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = GENMASK(13, 4) | BIT(1) },
4669 [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
4670 [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = GENMASK(5, 4) | BIT(1) },
4671 [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
4672 [GCC_UNIPHY2_SOFT_RESET] = { .reg = 0x56204, .bitmask = GENMASK(5, 4) | BIT(1) },
4673 [GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 },
4674 [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = GENMASK(21, 20) },
4675 [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = BIT(24) | GENMASK(1, 0) },
4676 [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = BIT(25) | GENMASK(3, 2) },
4677 [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = BIT(26) | GENMASK(5, 4) },
4678 [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = BIT(27) | GENMASK(9, 8) },
4679 [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = BIT(28) | GENMASK(11, 10) },
4680 [GCC_NSSPORT6_RESET] = { .reg = 0x68014, .bitmask = BIT(29) | GENMASK(13, 12) },
4698 .max_register = 0x7fffc,
4723 regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26)); in gcc_ipq8074_probe()