Lines Matching +full:0 +full:x29000
50 .offset = 0x21000,
53 .enable_reg = 0x0b000,
54 .enable_mask = BIT(0),
79 .offset = 0x21000,
98 { P_XO, 0 },
104 .offset = 0x25000,
108 .enable_reg = 0x0b000,
122 .offset = 0x25000,
136 .offset = 0x37000,
139 .enable_reg = 0x0b000,
153 .offset = 0x37000,
166 .offset = 0x24000,
169 .enable_reg = 0x0b000,
183 .offset = 0x24000,
196 F(24000000, P_XO, 1, 0, 0),
197 F(50000000, P_GPLL0, 16, 0, 0),
198 F(100000000, P_GPLL0, 8, 0, 0),
203 .cmd_rcgr = 0x27000,
216 .offset = 0x4a000,
219 .enable_reg = 0x0b000,
233 .offset = 0x4a000,
246 .offset = 0x22000,
249 .enable_reg = 0x0b000,
263 .offset = 0x22000,
276 F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
277 F(320000000, P_GPLL0, 2.5, 0, 0),
278 F(600000000, P_GPLL4, 2, 0, 0),
291 { P_XO, 0 },
299 .cmd_rcgr = 0x29064,
324 F(66670000, P_GPLL0_DIV2, 6, 0, 0),
325 F(240000000, P_GPLL4, 5, 0, 0),
330 .cmd_rcgr = 0x2900c,
356 F(24000000, P_XO, 1, 0, 0),
357 F(300000000, P_BIAS_PLL, 1, 0, 0),
371 { P_XO, 0 },
380 .cmd_rcgr = 0x68080,
393 .halt_reg = 0x30018,
395 .enable_reg = 0x30018,
410 F(24000000, P_XO, 1, 0, 0),
411 F(200000000, P_GPLL0, 4, 0, 0),
421 { P_XO, 0 },
426 .cmd_rcgr = 0x68098,
439 .halt_reg = 0x30000,
441 .enable_reg = 0x30000,
455 F(24000000, P_XO, 1, 0, 0),
456 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
457 F(100000000, P_GPLL0, 8, 0, 0),
458 F(133333333, P_GPLL0, 6, 0, 0),
459 F(160000000, P_GPLL0, 5, 0, 0),
460 F(200000000, P_GPLL0, 4, 0, 0),
461 F(266666667, P_GPLL0, 3, 0, 0),
474 { P_XO, 0 },
481 .cmd_rcgr = 0x76054,
494 F(24000000, P_XO, 1, 0, 0),
495 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
496 F(50000000, P_GPLL0, 16, 0, 0),
497 F(100000000, P_GPLL0, 8, 0, 0),
502 .cmd_rcgr = 0x46000,
515 F(24000000, P_XO, 1, 0, 0),
516 F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
517 F(25000000, P_UNIPHY0_RX, 5, 0, 0),
518 F(78125000, P_UNIPHY1_RX, 4, 0, 0),
519 F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
520 F(125000000, P_UNIPHY0_RX, 1, 0, 0),
521 F(156250000, P_UNIPHY1_RX, 2, 0, 0),
522 F(312500000, P_UNIPHY1_RX, 1, 0, 0),
539 { P_XO, 0 },
549 .cmd_rcgr = 0x68060,
562 F(24000000, P_XO, 1, 0, 0),
563 F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
564 F(25000000, P_UNIPHY0_TX, 5, 0, 0),
565 F(78125000, P_UNIPHY1_TX, 4, 0, 0),
566 F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
567 F(125000000, P_UNIPHY0_TX, 1, 0, 0),
568 F(156250000, P_UNIPHY1_TX, 2, 0, 0),
569 F(312500000, P_UNIPHY1_TX, 1, 0, 0),
586 { P_XO, 0 },
596 .cmd_rcgr = 0x68068,
609 F(24000000, P_XO, 1, 0, 0),
610 F(200000000, P_GPLL0, 4, 0, 0),
611 F(240000000, P_GPLL4, 5, 0, 0),
616 F(24000000, P_XO, 1, 0, 0),
617 F(100000000, P_GPLL0, 8, 0, 0),
628 { P_XO, 0 },
634 .cmd_rcgr = 0x75054,
647 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
648 F(100000000, P_GPLL0, 8, 0, 0),
649 F(133330000, P_GPLL0, 6, 0, 0),
650 F(200000000, P_GPLL0, 4, 0, 0),
661 { P_XO, 0 },
667 .cmd_rcgr = 0x3e00c,
681 .reg = 0x46018,
709 F(24000000, P_XO, 1, 0, 0),
710 F(25000000, P_UNIPHY0_RX, 5, 0, 0),
711 F(125000000, P_UNIPHY0_RX, 1, 0, 0),
724 { P_XO, 0 },
732 .cmd_rcgr = 0x68020,
745 F(24000000, P_XO, 1, 0, 0),
746 F(25000000, P_UNIPHY0_TX, 5, 0, 0),
747 F(125000000, P_UNIPHY0_TX, 1, 0, 0),
760 { P_XO, 0 },
768 .cmd_rcgr = 0x68028,
781 .cmd_rcgr = 0x68030,
794 .cmd_rcgr = 0x68038,
807 .cmd_rcgr = 0x68040,
820 .cmd_rcgr = 0x68048,
833 .cmd_rcgr = 0x68050,
846 .cmd_rcgr = 0x68058,
859 .reg = 0x68440,
860 .shift = 0,
875 .reg = 0x68444,
876 .shift = 0,
891 F(24000000, P_XO, 1, 0, 0),
892 F(100000000, P_GPLL0_DIV2, 4, 0, 0),
893 F(200000000, P_GPLL0, 4, 0, 0),
894 F(308570000, P_GPLL6, 3.5, 0, 0),
895 F(400000000, P_GPLL0, 2, 0, 0),
896 F(533000000, P_GPLL0, 1.5, 0, 0),
910 { P_XO, 0 },
918 .cmd_rcgr = 0x38048,
931 F(24000000, P_XO, 1, 0, 0),
932 F(300000000, P_NSS_CRYPTO_PLL, 2, 0, 0),
943 { P_XO, 0 },
949 .cmd_rcgr = 0x68144,
963 .reg = 0x68400,
964 .shift = 0,
979 .reg = 0x68404,
980 .shift = 0,
995 .reg = 0x68410,
996 .shift = 0,
1011 .reg = 0x68414,
1012 .shift = 0,
1027 .reg = 0x68420,
1028 .shift = 0,
1043 .reg = 0x68424,
1044 .shift = 0,
1059 .reg = 0x68430,
1060 .shift = 0,
1075 .reg = 0x68434,
1076 .shift = 0,
1091 F(24000000, P_XO, 1, 0, 0),
1092 F(149760000, P_UBI32_PLL, 10, 0, 0),
1093 F(187200000, P_UBI32_PLL, 8, 0, 0),
1094 F(249600000, P_UBI32_PLL, 6, 0, 0),
1095 F(374400000, P_UBI32_PLL, 4, 0, 0),
1096 F(748800000, P_UBI32_PLL, 2, 0, 0),
1097 F(1497600000, P_UBI32_PLL, 1, 0, 0),
1112 { P_XO, 0 },
1121 .cmd_rcgr = 0x68104,
1135 F(24000000, P_XO, 1, 0, 0),
1136 F(100000000, P_GPLL0, 8, 0, 0),
1141 .cmd_rcgr = 0x1c008,
1154 F(24000000, P_XO, 1, 0, 0),
1155 F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1156 F(50000000, P_GPLL0, 16, 0, 0),
1161 .cmd_rcgr = 0x0200c,
1175 F(4800000, P_XO, 5, 0, 0),
1179 F(24000000, P_XO, 1, 0, 0),
1181 F(50000000, P_GPLL0, 16, 0, 0),
1186 .cmd_rcgr = 0x02024,
1200 .cmd_rcgr = 0x03000,
1213 .cmd_rcgr = 0x03014,
1227 .cmd_rcgr = 0x04000,
1240 .cmd_rcgr = 0x04014,
1254 .cmd_rcgr = 0x05000,
1267 .cmd_rcgr = 0x05014,
1281 .cmd_rcgr = 0x06000,
1294 .cmd_rcgr = 0x06014,
1308 .cmd_rcgr = 0x07000,
1321 .cmd_rcgr = 0x07014,
1339 F(24000000, P_XO, 1, 0, 0),
1355 .cmd_rcgr = 0x02044,
1369 .cmd_rcgr = 0x03034,
1383 .cmd_rcgr = 0x04034,
1397 .cmd_rcgr = 0x05034,
1411 .cmd_rcgr = 0x06034,
1425 .cmd_rcgr = 0x07034,
1439 F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1440 F(80000000, P_GPLL0, 10, 0, 0),
1441 F(100000000, P_GPLL0, 8, 0, 0),
1442 F(160000000, P_GPLL0, 5, 0, 0),
1447 .cmd_rcgr = 0x16004,
1460 F(24000000, P_XO, 1, 0, 0),
1461 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1462 F(100000000, P_GPLL0, 8, 0, 0),
1463 F(200000000, P_GPLL0, 4, 0, 0),
1464 F(266666666, P_GPLL0, 3, 0, 0),
1477 { P_XO, 0 },
1485 .cmd_rcgr = 0x08004,
1499 .cmd_rcgr = 0x09004,
1513 .cmd_rcgr = 0x0a004,
1540 .reg = 0x68118,
1541 .shift = 0,
1556 F(24000000, P_XO, 1, 0, 0),
1566 { P_XO, 0 },
1572 .cmd_rcgr = 0x75024,
1591 { P_PCIE20_PHY0_PIPE, 0 },
1596 .reg = 0x7501c,
1616 F(96000000, P_GPLL2, 12, 0, 0),
1617 F(177777778, P_GPLL0, 4.5, 0, 0),
1618 F(192000000, P_GPLL2, 6, 0, 0),
1619 F(384000000, P_GPLL2, 3, 0, 0),
1632 { P_XO, 0 },
1639 .cmd_rcgr = 0x42004,
1653 F(24000000, P_XO, 1, 0, 0),
1658 .cmd_rcgr = 0x3e05c,
1672 F(24000000, P_XO, 1, 0, 0),
1686 { P_XO, 0 },
1693 .cmd_rcgr = 0x3e020,
1712 { P_USB3PHY_0_PIPE, 0 },
1717 .reg = 0x3e048,
1733 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1734 F(160000000, P_GPLL0, 5, 0, 0),
1735 F(216000000, P_GPLL6, 5, 0, 0),
1736 F(308570000, P_GPLL6, 3.5, 0, 0),
1747 { P_XO, 0 },
1754 .cmd_rcgr = 0x5d000,
1768 F(24000000, P_XO, 1, 0, 0),
1769 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1770 F(100000000, P_GPLL0, 8, 0, 0),
1771 F(200000000, P_GPLL0, 4, 0, 0),
1776 .cmd_rcgr = 0x2902C,
1789 F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1790 F(160000000, P_GPLL0, 5, 0, 0),
1791 F(300000000, P_GPLL4, 4, 0, 0),
1803 { P_XO, 0 },
1810 .cmd_rcgr = 0x29048,
1823 .cmd_rcgr = 0x3f020,
1837 .halt_reg = 0x1c020,
1839 .enable_reg = 0x1c020,
1840 .enable_mask = BIT(0),
1853 .halt_reg = 0x4601c,
1856 .enable_reg = 0x0b004,
1870 F(24000000, P_XO, 1, 0, 0),
1871 F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1872 F(100000000, P_GPLL0, 8, 0, 0),
1873 F(133333333, P_GPLL0, 6, 0, 0),
1874 F(160000000, P_GPLL0, 5, 0, 0),
1875 F(200000000, P_GPLL0, 4, 0, 0),
1876 F(266666667, P_GPLL0, 3, 0, 0),
1881 .cmd_rcgr = 0x26004,
1894 F(24000000, P_XO, 1, 0, 0),
1895 F(307670000, P_BIAS_PLL_NSS_NOC, 1.5, 0, 0),
1896 F(533333333, P_GPLL0, 1.5, 0, 0),
1909 { P_XO, 0 },
1916 .cmd_rcgr = 0x68088,
1929 .halt_reg = 0x46020,
1932 .enable_reg = 0x0b004,
1946 .halt_reg = 0x01008,
1949 .enable_reg = 0x0b004,
1963 .halt_reg = 0x02008,
1965 .enable_reg = 0x02008,
1966 .enable_mask = BIT(0),
1979 .halt_reg = 0x02004,
1981 .enable_reg = 0x02004,
1982 .enable_mask = BIT(0),
1995 .halt_reg = 0x03010,
1997 .enable_reg = 0x03010,
1998 .enable_mask = BIT(0),
2011 .halt_reg = 0x0300c,
2013 .enable_reg = 0x0300c,
2014 .enable_mask = BIT(0),
2027 .halt_reg = 0x04010,
2029 .enable_reg = 0x04010,
2030 .enable_mask = BIT(0),
2043 .halt_reg = 0x0400c,
2045 .enable_reg = 0x0400c,
2046 .enable_mask = BIT(0),
2059 .halt_reg = 0x05010,
2061 .enable_reg = 0x05010,
2062 .enable_mask = BIT(0),
2075 .halt_reg = 0x0500c,
2077 .enable_reg = 0x0500c,
2078 .enable_mask = BIT(0),
2091 .halt_reg = 0x06010,
2093 .enable_reg = 0x06010,
2094 .enable_mask = BIT(0),
2107 .halt_reg = 0x0600c,
2109 .enable_reg = 0x0600c,
2110 .enable_mask = BIT(0),
2123 .halt_reg = 0x07010,
2125 .enable_reg = 0x07010,
2126 .enable_mask = BIT(0),
2143 .halt_reg = 0x0700c,
2145 .enable_reg = 0x0700c,
2146 .enable_mask = BIT(0),
2159 .halt_reg = 0x0203c,
2161 .enable_reg = 0x0203c,
2162 .enable_mask = BIT(0),
2175 .halt_reg = 0x0302c,
2177 .enable_reg = 0x0302c,
2178 .enable_mask = BIT(0),
2191 .halt_reg = 0x0402c,
2193 .enable_reg = 0x0402c,
2194 .enable_mask = BIT(0),
2207 .halt_reg = 0x0502c,
2209 .enable_reg = 0x0502c,
2210 .enable_mask = BIT(0),
2223 .halt_reg = 0x0602c,
2225 .enable_reg = 0x0602c,
2226 .enable_mask = BIT(0),
2239 .halt_reg = 0x0702c,
2241 .enable_reg = 0x0702c,
2242 .enable_mask = BIT(0),
2255 .halt_reg = 0x16024,
2258 .enable_reg = 0x0b004,
2259 .enable_mask = BIT(0),
2272 .halt_reg = 0x16020,
2275 .enable_reg = 0x0b004,
2289 .halt_reg = 0x1601c,
2292 .enable_reg = 0x0b004,
2319 .halt_reg = 0x30030,
2321 .enable_reg = 0x30030,
2322 .enable_mask = BIT(0),
2335 .halt_reg = 0x08000,
2337 .enable_reg = 0x08000,
2338 .enable_mask = BIT(0),
2351 .halt_reg = 0x09000,
2353 .enable_reg = 0x09000,
2354 .enable_mask = BIT(0),
2367 .halt_reg = 0x0a000,
2369 .enable_reg = 0x0a000,
2370 .enable_mask = BIT(0),
2383 .halt_reg = 0x58004,
2385 .enable_reg = 0x58004,
2386 .enable_mask = BIT(0),
2399 .halt_reg = 0x68310,
2401 .enable_reg = 0x68310,
2402 .enable_mask = BIT(0),
2415 .halt_reg = 0x68174,
2417 .enable_reg = 0x68174,
2418 .enable_mask = BIT(0),
2431 .halt_reg = 0x68170,
2433 .enable_reg = 0x68170,
2434 .enable_mask = BIT(0),
2447 .halt_reg = 0x68160,
2449 .enable_reg = 0x68160,
2450 .enable_mask = BIT(0),
2463 .halt_reg = 0x68164,
2465 .enable_reg = 0x68164,
2466 .enable_mask = BIT(0),
2479 .halt_reg = 0x68318,
2481 .enable_reg = 0x68318,
2482 .enable_mask = BIT(0),
2495 .halt_reg = 0x6819C,
2497 .enable_reg = 0x6819C,
2498 .enable_mask = BIT(0),
2511 .halt_reg = 0x68198,
2513 .enable_reg = 0x68198,
2514 .enable_mask = BIT(0),
2527 .halt_reg = 0x68168,
2529 .enable_reg = 0x68168,
2530 .enable_mask = BIT(0),
2543 .halt_reg = 0x2606c,
2545 .enable_reg = 0x2606c,
2546 .enable_mask = BIT(0),
2559 .halt_reg = 0x26070,
2561 .enable_reg = 0x26070,
2562 .enable_mask = BIT(0),
2575 F(24000000, P_XO, 1, 0, 0),
2576 F(133333333, P_GPLL0, 6, 0, 0),
2581 F(24000000, P_XO, 1, 0, 0),
2582 F(400000000, P_GPLL0, 2, 0, 0),
2587 .cmd_rcgr = 0x59020,
2608 { P_XO, 0 },
2616 .cmd_rcgr = 0x59120,
2629 F(24000000, P_XO, 1, 0, 0),
2630 F(100000000, P_GPLL0, 8, 0, 0),
2635 .cmd_rcgr = 0x1F020,
2648 F(24000000, P_XO, 1, 0, 0),
2649 F(266666667, P_GPLL0, 3, 0, 0),
2654 .cmd_rcgr = 0x1F040,
2667 F(24000000, P_XO, 1, 0, 0),
2668 F(400000000, P_GPLL0, 2, 0, 0),
2673 .cmd_rcgr = 0x1F008,
2686 F(24000000, P_XO, 1, 0, 0),
2687 F(50000000, P_GPLL0, 16, 0, 0),
2692 .cmd_rcgr = 0x3a00c,
2705 .halt_reg = 0x1F028,
2707 .enable_reg = 0x1F028,
2708 .enable_mask = BIT(0),
2721 .halt_reg = 0x1F048,
2723 .enable_reg = 0x1F048,
2724 .enable_mask = BIT(0),
2737 .halt_reg = 0x1F010,
2739 .enable_reg = 0x1F010,
2740 .enable_mask = BIT(0),
2753 .halt_reg = 0x1F018,
2755 .enable_reg = 0x1F018,
2756 .enable_mask = BIT(0),
2769 .halt_reg = 0x1F01C,
2771 .enable_reg = 0x1F01C,
2772 .enable_mask = BIT(0),
2785 .halt_reg = 0x1F014,
2787 .enable_reg = 0x1F014,
2788 .enable_mask = BIT(0),
2801 .halt_reg = 0x1F038,
2803 .enable_reg = 0x1F038,
2804 .enable_mask = BIT(0),
2817 .halt_reg = 0x12094,
2819 .enable_reg = 0xb00c,
2833 .halt_reg = 0x27020,
2835 .enable_reg = 0x27020,
2836 .enable_mask = BIT(0),
2849 .halt_reg = 0x1D044,
2851 .enable_reg = 0x1D044,
2852 .enable_mask = BIT(0),
2865 .halt_reg = 0x26074,
2867 .enable_reg = 0x26074,
2868 .enable_mask = BIT(0),
2881 .halt_reg = 0x1D03C,
2883 .enable_reg = 0x1D03C,
2884 .enable_mask = BIT(0),
2897 .halt_reg = 0x68240,
2899 .enable_reg = 0x68240,
2900 .enable_mask = BIT(0),
2913 .halt_reg = 0x68244,
2915 .enable_reg = 0x68244,
2916 .enable_mask = BIT(0),
2929 .halt_reg = 0x68248,
2931 .enable_reg = 0x68248,
2932 .enable_mask = BIT(0),
2945 .halt_reg = 0x6824c,
2947 .enable_reg = 0x6824c,
2948 .enable_mask = BIT(0),
2961 .halt_reg = 0x68250,
2963 .enable_reg = 0x68250,
2964 .enable_mask = BIT(0),
2977 .halt_reg = 0x68254,
2979 .enable_reg = 0x68254,
2980 .enable_mask = BIT(0),
2993 .halt_reg = 0x68258,
2995 .enable_reg = 0x68258,
2996 .enable_mask = BIT(0),
3009 .halt_reg = 0x6825c,
3011 .enable_reg = 0x6825c,
3012 .enable_mask = BIT(0),
3025 .halt_reg = 0x68260,
3027 .enable_reg = 0x68260,
3028 .enable_mask = BIT(0),
3041 .halt_reg = 0x68264,
3043 .enable_reg = 0x68264,
3044 .enable_mask = BIT(0),
3057 .halt_reg = 0x68194,
3059 .enable_reg = 0x68194,
3060 .enable_mask = BIT(0),
3073 .halt_reg = 0x68190,
3075 .enable_reg = 0x68190,
3076 .enable_mask = BIT(0),
3089 .halt_reg = 0x68338,
3091 .enable_reg = 0x68338,
3092 .enable_mask = BIT(0),
3105 .halt_reg = 0x6816C,
3107 .enable_reg = 0x6816C,
3108 .enable_mask = BIT(0),
3121 .halt_reg = 0x6830C,
3123 .enable_reg = 0x6830C,
3124 .enable_mask = BIT(0),
3137 .halt_reg = 0x68308,
3139 .enable_reg = 0x68308,
3140 .enable_mask = BIT(0),
3153 .halt_reg = 0x68314,
3155 .enable_reg = 0x68314,
3156 .enable_mask = BIT(0),
3169 .halt_reg = 0x68304,
3171 .enable_reg = 0x68304,
3172 .enable_mask = BIT(0),
3184 .halt_reg = 0x68300,
3186 .enable_reg = 0x68300,
3187 .enable_mask = BIT(0),
3200 .halt_reg = 0x68180,
3202 .enable_reg = 0x68180,
3203 .enable_mask = BIT(0),
3216 .halt_reg = 0x68188,
3218 .enable_reg = 0x68188,
3219 .enable_mask = BIT(0),
3232 .halt_reg = 0x68184,
3234 .enable_reg = 0x68184,
3235 .enable_mask = BIT(0),
3248 .halt_reg = 0x68270,
3250 .enable_reg = 0x68270,
3251 .enable_mask = BIT(0),
3264 .halt_reg = 0x68320,
3266 .enable_reg = 0x68320,
3267 .enable_mask = BIT(0),
3280 .halt_reg = 0x68324,
3282 .enable_reg = 0x68324,
3283 .enable_mask = BIT(0),
3296 .halt_reg = 0x68328,
3298 .enable_reg = 0x68328,
3299 .enable_mask = BIT(0),
3312 .halt_reg = 0x6832c,
3314 .enable_reg = 0x6832c,
3315 .enable_mask = BIT(0),
3328 .halt_reg = 0x68330,
3330 .enable_reg = 0x68330,
3331 .enable_mask = BIT(0),
3344 .halt_reg = 0x6820C,
3347 .enable_reg = 0x6820C,
3348 .enable_mask = BIT(0),
3361 .halt_reg = 0x68200,
3364 .enable_reg = 0x68200,
3365 .enable_mask = BIT(0),
3378 .halt_reg = 0x68204,
3381 .enable_reg = 0x68204,
3382 .enable_mask = BIT(0),
3395 .halt_reg = 0x68210,
3398 .enable_reg = 0x68210,
3399 .enable_mask = BIT(0),
3412 .halt_reg = 0x75010,
3414 .enable_reg = 0x75010,
3415 .enable_mask = BIT(0),
3428 .halt_reg = 0x75014,
3430 .enable_reg = 0x75014,
3431 .enable_mask = BIT(0),
3444 .halt_reg = 0x75008,
3446 .enable_reg = 0x75008,
3447 .enable_mask = BIT(0),
3460 .halt_reg = 0x7500c,
3462 .enable_reg = 0x7500c,
3463 .enable_mask = BIT(0),
3476 .halt_reg = 0x26048,
3478 .enable_reg = 0x26048,
3479 .enable_mask = BIT(0),
3492 .halt_reg = 0x75018,
3495 .enable_reg = 0x75018,
3496 .enable_mask = BIT(0),
3509 .halt_reg = 0x13004,
3512 .enable_reg = 0x0b004,
3526 .halt_reg = 0x29084,
3528 .enable_reg = 0x29084,
3529 .enable_mask = BIT(0),
3542 .halt_reg = 0x57024,
3544 .enable_reg = 0x57024,
3545 .enable_mask = BIT(0),
3558 .halt_reg = 0x57020,
3560 .enable_reg = 0x57020,
3561 .enable_mask = BIT(0),
3574 .halt_reg = 0x4201c,
3576 .enable_reg = 0x4201c,
3577 .enable_mask = BIT(0),
3590 .halt_reg = 0x42018,
3592 .enable_reg = 0x42018,
3593 .enable_mask = BIT(0),
3606 .halt_reg = 0x56008,
3608 .enable_reg = 0x56008,
3609 .enable_mask = BIT(0),
3622 .halt_reg = 0x56010,
3624 .enable_reg = 0x56010,
3625 .enable_mask = BIT(0),
3638 .halt_reg = 0x56014,
3640 .enable_reg = 0x56014,
3641 .enable_mask = BIT(0),
3654 .halt_reg = 0x56018,
3656 .enable_reg = 0x56018,
3657 .enable_mask = BIT(0),
3670 .halt_reg = 0x5601c,
3672 .enable_reg = 0x5601c,
3673 .enable_mask = BIT(0),
3686 .halt_reg = 0x56020,
3688 .enable_reg = 0x56020,
3689 .enable_mask = BIT(0),
3702 .halt_reg = 0x56024,
3704 .enable_reg = 0x56024,
3705 .enable_mask = BIT(0),
3718 .halt_reg = 0x56028,
3720 .enable_reg = 0x56028,
3721 .enable_mask = BIT(0),
3734 .halt_reg = 0x5602c,
3736 .enable_reg = 0x5602c,
3737 .enable_mask = BIT(0),
3750 .halt_reg = 0x56030,
3752 .enable_reg = 0x56030,
3753 .enable_mask = BIT(0),
3766 .halt_reg = 0x56034,
3768 .enable_reg = 0x56034,
3769 .enable_mask = BIT(0),
3782 .halt_reg = 0x5600C,
3784 .enable_reg = 0x5600C,
3785 .enable_mask = BIT(0),
3798 .halt_reg = 0x56108,
3800 .enable_reg = 0x56108,
3801 .enable_mask = BIT(0),
3814 .halt_reg = 0x56110,
3816 .enable_reg = 0x56110,
3817 .enable_mask = BIT(0),
3830 .halt_reg = 0x56114,
3832 .enable_reg = 0x56114,
3833 .enable_mask = BIT(0),
3846 .halt_reg = 0x5610C,
3848 .enable_reg = 0x5610C,
3849 .enable_mask = BIT(0),
3862 .halt_reg = 0x3e044,
3864 .enable_reg = 0x3e044,
3865 .enable_mask = BIT(0),
3878 .halt_reg = 0x3e000,
3880 .enable_reg = 0x3e000,
3881 .enable_mask = BIT(0),
3894 .halt_reg = 0x47014,
3896 .enable_reg = 0x47014,
3897 .enable_mask = BIT(0),
3910 .cmd_rcgr = 0x75070,
3923 .halt_reg = 0x75070,
3925 .enable_reg = 0x75070,
3939 .halt_reg = 0x75048,
3941 .enable_reg = 0x75048,
3942 .enable_mask = BIT(0),
3955 .halt_reg = 0x26040,
3957 .enable_reg = 0x26040,
3958 .enable_mask = BIT(0),
3971 .halt_reg = 0x3e008,
3973 .enable_reg = 0x3e008,
3974 .enable_mask = BIT(0),
3987 .halt_reg = 0x3e080,
3989 .enable_reg = 0x3e080,
3990 .enable_mask = BIT(0),
4003 .halt_reg = 0x3e040,
4006 .enable_reg = 0x3e040,
4007 .enable_mask = BIT(0),
4020 .halt_reg = 0x3e004,
4022 .enable_reg = 0x3e004,
4023 .enable_mask = BIT(0),
4036 .halt_reg = 0x3f000,
4038 .enable_reg = 0x3f000,
4039 .enable_mask = BIT(0),
4052 .halt_reg = 0x3f008,
4054 .enable_reg = 0x3f008,
4055 .enable_mask = BIT(0),
4068 .halt_reg = 0x3f080,
4070 .enable_reg = 0x3f080,
4071 .enable_mask = BIT(0),
4084 .halt_reg = 0x3f004,
4086 .enable_reg = 0x3f004,
4087 .enable_mask = BIT(0),
4100 .halt_reg = 0x56308,
4102 .enable_reg = 0x56308,
4103 .enable_mask = BIT(0),
4116 .halt_reg = 0x5630c,
4118 .enable_reg = 0x5630c,
4119 .enable_mask = BIT(0),
4132 .halt_reg = 0x5d014,
4134 .enable_reg = 0x5d014,
4135 .enable_mask = BIT(0),
4148 .halt_reg = 0x77004,
4150 .enable_reg = 0x77004,
4151 .enable_mask = BIT(0),
4164 .l = 0x3e,
4165 .alpha = 0x6667,
4166 .config_ctl_val = 0x240d4828,
4167 .config_ctl_hi_val = 0x6,
4168 .main_output_mask = BIT(0),
4170 .pre_div_val = 0x0,
4172 .post_div_val = 0x0,
4175 .test_ctl_val = 0x1C0000C0,
4176 .test_ctl_hi_val = 0x4000,
4180 .l = 0x32,
4181 .alpha = 0x0,
4182 .alpha_hi = 0x0,
4183 .config_ctl_val = 0x4001055b,
4184 .main_output_mask = BIT(0),
4185 .pre_div_val = 0x0,
4187 .post_div_val = 0x1 << 8,
4190 .vco_val = 0x0,
4428 [GCC_BLSP1_BCR] = { 0x01000, 0 },
4429 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4430 [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4431 [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4432 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4433 [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4434 [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4435 [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4436 [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4437 [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4438 [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4439 [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4440 [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4441 [GCC_IMEM_BCR] = { 0x0e000, 0 },
4442 [GCC_SMMU_BCR] = { 0x12000, 0 },
4443 [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4444 [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4445 [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4446 [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4447 [GCC_PRNG_BCR] = { 0x13000, 0 },
4448 [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4449 [GCC_CRYPTO_BCR] = { 0x16000, 0 },
4450 [GCC_WCSS_BCR] = { 0x18000, 0 },
4451 [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4452 [GCC_NSS_BCR] = { 0x19000, 0 },
4453 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4454 [GCC_ADSS_BCR] = { 0x1c000, 0 },
4455 [GCC_DDRSS_BCR] = { 0x1e000, 0 },
4456 [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4457 [GCC_PCNOC_BCR] = { 0x27018, 0 },
4458 [GCC_TCSR_BCR] = { 0x28000, 0 },
4459 [GCC_QDSS_BCR] = { 0x29000, 0 },
4460 [GCC_DCD_BCR] = { 0x2a000, 0 },
4461 [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4462 [GCC_MPM_BCR] = { 0x2c000, 0 },
4463 [GCC_SPDM_BCR] = { 0x2f000, 0 },
4464 [GCC_RBCPR_BCR] = { 0x33000, 0 },
4465 [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4466 [GCC_TLMM_BCR] = { 0x34000, 0 },
4467 [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4468 [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4469 [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4470 [GCC_USB0_BCR] = { 0x3e070, 0 },
4471 [GCC_USB1_BCR] = { 0x3f070, 0 },
4472 [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4473 [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4474 [GCC_SDCC1_BCR] = { 0x42000, 0 },
4475 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4476 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x47008, 0 },
4477 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47010, 0 },
4478 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4479 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4480 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4481 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4482 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4483 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4484 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4485 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4486 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4487 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4488 [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4489 [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4490 [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4491 [GCC_QPIC_BCR] = { 0x57018, 0 },
4492 [GCC_MDIO_BCR] = { 0x58000, 0 },
4493 [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4494 [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4495 [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4496 [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4497 [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4498 [GCC_PCIE0_BCR] = { 0x75004, 0 },
4499 [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4500 [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4501 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4502 [GCC_DCC_BCR] = { 0x77000, 0 },
4503 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4504 [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4505 [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4506 [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4507 [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4508 [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4509 [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4510 [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4511 [GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
4512 [GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
4513 [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4514 [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4515 [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4516 [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4517 [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4518 [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4519 [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4520 [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4521 [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4522 [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4523 [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4524 [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4525 [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4526 [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4527 [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4528 [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4529 [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4530 [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4531 [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4532 [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4533 [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4534 [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
4535 [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = 0xf0000 },
4536 [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = 0x3ff2 },
4537 [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
4538 [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = 0x32 },
4539 [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
4540 [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = 0x300000 },
4541 [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = 0x1000003 },
4542 [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = 0x200000c },
4543 [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = 0x4000030 },
4544 [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = 0x8000300 },
4545 [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = 0x10000c00 },
4546 [GCC_UNIPHY0_PORT1_ARES] = { .reg = 0x56004, .bitmask = 0x30 },
4547 [GCC_UNIPHY0_PORT2_ARES] = { .reg = 0x56004, .bitmask = 0xc0 },
4548 [GCC_UNIPHY0_PORT3_ARES] = { .reg = 0x56004, .bitmask = 0x300 },
4549 [GCC_UNIPHY0_PORT4_ARES] = { .reg = 0x56004, .bitmask = 0xc00 },
4550 [GCC_UNIPHY0_PORT5_ARES] = { .reg = 0x56004, .bitmask = 0x3000 },
4551 [GCC_UNIPHY0_PORT_4_5_RESET] = { .reg = 0x56004, .bitmask = 0x3c02 },
4552 [GCC_UNIPHY0_PORT_4_RESET] = { .reg = 0x56004, .bitmask = 0xc02 },
4553 [GCC_LPASS_BCR] = {0x1F000, 0},
4554 [GCC_UBI32_TBU_BCR] = {0x65000, 0},
4555 [GCC_LPASS_TBU_BCR] = {0x6C000, 0},
4556 [GCC_WCSSAON_RESET] = {0x59010, 0},
4557 [GCC_LPASS_Q6_AXIM_ARES] = {0x1F004, 0},
4558 [GCC_LPASS_Q6SS_TSCTR_1TO2_ARES] = {0x1F004, 1},
4559 [GCC_LPASS_Q6SS_TRIG_ARES] = {0x1F004, 2},
4560 [GCC_LPASS_Q6_ATBM_AT_ARES] = {0x1F004, 3},
4561 [GCC_LPASS_Q6_PCLKDBG_ARES] = {0x1F004, 4},
4562 [GCC_LPASS_CORE_AXIM_ARES] = {0x1F004, 5},
4563 [GCC_LPASS_SNOC_CFG_ARES] = {0x1F004, 6},
4564 [GCC_WCSS_DBG_ARES] = {0x59008, 0},
4565 [GCC_WCSS_ECAHB_ARES] = {0x59008, 1},
4566 [GCC_WCSS_ACMT_ARES] = {0x59008, 2},
4567 [GCC_WCSS_DBG_BDG_ARES] = {0x59008, 3},
4568 [GCC_WCSS_AHB_S_ARES] = {0x59008, 4},
4569 [GCC_WCSS_AXI_M_ARES] = {0x59008, 5},
4570 [GCC_Q6SS_DBG_ARES] = {0x59110, 0},
4571 [GCC_Q6_AHB_S_ARES] = {0x59110, 1},
4572 [GCC_Q6_AHB_ARES] = {0x59110, 2},
4573 [GCC_Q6_AXIM2_ARES] = {0x59110, 3},
4574 [GCC_Q6_AXIM_ARES] = {0x59110, 4},
4587 .max_register = 0x7fffc,
4610 regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0); in gcc_ipq6018_probe()
4612 regmap_update_bits(regmap, 0x3e078, BIT(2), BIT(2)); in gcc_ipq6018_probe()
4614 regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0); in gcc_ipq6018_probe()
4616 regmap_update_bits(regmap, 0x3f078, BIT(2), BIT(2)); in gcc_ipq6018_probe()
4619 regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26)); in gcc_ipq6018_probe()