Lines Matching +full:0 +full:x29000
62 .offset = 0x21000,
65 .enable_reg = 0x0b000,
66 .enable_mask = BIT(0),
77 .offset = 0x4a000,
80 .enable_reg = 0x0b000,
92 .offset = 0x24000,
95 .enable_reg = 0x0b000,
107 .offset = 0x25000,
110 .enable_reg = 0x0b000,
122 .offset = 0x21000,
136 .offset = 0x4a000,
150 .offset = 0x24000,
164 .offset = 0x25000,
199 { P_XO, 0 },
210 { P_XO, 0 },
221 { P_XO, 0 },
233 { P_XO, 0 },
245 { P_XO, 0 },
258 { P_XO, 0 },
271 { P_XO, 0 },
283 { P_XO, 0 },
296 { P_XO, 0 },
310 { P_XO, 0 },
324 { P_XO, 0 },
331 { P_XO, 0 },
346 { P_XO, 0 },
362 { P_XO, 0 },
378 { P_XO, 0 },
394 { P_XO, 0 },
407 { P_PCIE20_PHY0_PIPE, 0 },
417 { P_PCIE20_PHY1_PIPE, 0 },
427 { P_USB3PHY_0_PIPE, 0 },
432 F(24000000, P_XO, 1, 0, 0),
433 F(100000000, P_GPLL0, 8, 0, 0),
438 .cmd_rcgr = 0x1f008,
451 F(50000000, P_GPLL0, 16, 0, 0),
456 .cmd_rcgr = 0x0200c,
469 .cmd_rcgr = 0x03000,
482 .cmd_rcgr = 0x04000,
496 F(4800000, P_XO, 5, 0, 0),
499 F(24000000, P_XO, 1, 0, 0),
500 F(50000000, P_GPLL0, 16, 0, 0),
505 .cmd_rcgr = 0x02024,
519 .cmd_rcgr = 0x03014,
533 .cmd_rcgr = 0x04014,
550 F(24000000, P_XO, 1, 0, 0),
564 .cmd_rcgr = 0x02044,
578 .cmd_rcgr = 0x03034,
592 F(160000000, P_GPLL0, 5, 0, 0),
597 .cmd_rcgr = 0x16004,
610 F(2500000, P_GEPHY_TX, 5, 0, 0),
611 F(24000000, P_XO, 1, 0, 0),
612 F(25000000, P_GEPHY_TX, 5, 0, 0),
613 F(125000000, P_GEPHY_TX, 1, 0, 0),
618 .cmd_rcgr = 0x68020,
631 .reg = 0x68420,
632 .shift = 0,
648 .cmd_rcgr = 0x68028,
661 .reg = 0x68424,
662 .shift = 0,
678 F(2500000, P_UNIPHY_RX, 12.5, 0, 0),
679 F(24000000, P_XO, 1, 0, 0),
680 F(25000000, P_UNIPHY_RX, 2.5, 0, 0),
681 F(125000000, P_UNIPHY_RX, 2.5, 0, 0),
682 F(125000000, P_UNIPHY_RX, 1, 0, 0),
683 F(312500000, P_UNIPHY_RX, 1, 0, 0),
688 .cmd_rcgr = 0x68030,
701 .reg = 0x68430,
702 .shift = 0,
718 F(2500000, P_UNIPHY_TX, 12.5, 0, 0),
719 F(24000000, P_XO, 1, 0, 0),
720 F(25000000, P_UNIPHY_TX, 2.5, 0, 0),
721 F(125000000, P_UNIPHY_TX, 2.5, 0, 0),
722 F(125000000, P_UNIPHY_TX, 1, 0, 0),
723 F(312500000, P_UNIPHY_TX, 1, 0, 0),
728 .cmd_rcgr = 0x68038,
741 .reg = 0x68434,
742 .shift = 0,
758 F(240000000, P_GPLL4, 5, 0, 0),
763 .cmd_rcgr = 0x68080,
776 F(200000000, P_GPLL0, 4, 0, 0),
781 .cmd_rcgr = 0x08004,
795 .cmd_rcgr = 0x09004,
809 .cmd_rcgr = 0x0a004,
823 F(133333334, P_GPLL0, 6, 0, 0),
828 .cmd_rcgr = 0x2e028,
841 F(66666667, P_GPLL0, 12, 0, 0),
846 .cmd_rcgr = 0x2e040,
859 F(2000000, P_XO, 12, 0, 0),
863 .cmd_rcgr = 0x75020,
877 F(240000000, P_GPLL4, 5, 0, 0),
882 .cmd_rcgr = 0x75050,
895 .cmd_rcgr = 0x76020,
909 .cmd_rcgr = 0x76050,
922 .reg = 0x7501c,
938 .reg = 0x7601c,
953 F(100000000, P_GPLL0, 8, 0, 0),
958 .cmd_rcgr = 0x27000,
985 F(240000000, P_GPLL4, 5, 0, 0),
990 .cmd_rcgr = 0x2900c,
1003 F(200000000, P_GPLL0, 4, 0, 0),
1008 .cmd_rcgr = 0x2902c,
1021 F(266666667, P_GPLL0, 3, 0, 0),
1026 .cmd_rcgr = 0x29048,
1039 F(600000000, P_GPLL4, 2, 0, 0),
1044 .cmd_rcgr = 0x29064,
1098 F(24000000, P_XO, 1, 0, 0),
1099 F(100000000, P_GPLL0, 8, 0, 0),
1100 F(200000000, P_GPLL0, 4, 0, 0),
1101 F(320000000, P_GPLL0, 2.5, 0, 0),
1105 .cmd_rcgr = 0x57010,
1120 F(24000000, P_XO, 1, 0, 0),
1122 F(96000000, P_GPLL2, 12, 0, 0),
1124 F(192000000, P_GPLL2, 6, 0, 0),
1125 F(200000000, P_GPLL0, 4, 0, 0),
1130 .cmd_rcgr = 0x42004,
1144 F(266666667, P_GPLL0, 3, 0, 0),
1149 .cmd_rcgr = 0x26004,
1176 F(400000000, P_GPLL0, 2, 0, 0),
1181 .cmd_rcgr = 0x68088,
1195 F(850000000, P_UBI32_PLL, 1, 0, 0),
1196 F(1000000000, P_UBI32_PLL, 1, 0, 0),
1200 .cmd_rcgr = 0x68100,
1214 .cmd_rcgr = 0x3e05c,
1233 .cmd_rcgr = 0x3e090,
1247 .cmd_rcgr = 0x3e00c,
1266 .cmd_rcgr = 0x3e020,
1280 .reg = 0x3e048,
1296 F(400000000, P_GPLL0, 2, 0, 0),
1301 .cmd_rcgr = 0x59120,
1314 F(133333333, P_GPLL0, 6, 0, 0),
1319 .cmd_rcgr = 0x59020,
1332 .halt_reg = 0x30000,
1334 .enable_reg = 0x30000,
1346 .halt_reg = 0x30018,
1348 .enable_reg = 0x30018,
1361 .halt_reg = 0x30030,
1363 .enable_reg = 0x30030,
1364 .enable_mask = BIT(0),
1378 .halt_reg = 0x1f020,
1380 .enable_reg = 0x1f020,
1381 .enable_mask = BIT(0),
1395 .halt_reg = 0x01008,
1398 .enable_reg = 0x0b004,
1413 .halt_reg = 0x02008,
1415 .enable_reg = 0x02008,
1416 .enable_mask = BIT(0),
1430 .halt_reg = 0x02004,
1432 .enable_reg = 0x02004,
1433 .enable_mask = BIT(0),
1447 .halt_reg = 0x03010,
1449 .enable_reg = 0x03010,
1450 .enable_mask = BIT(0),
1464 .halt_reg = 0x0300c,
1466 .enable_reg = 0x0300c,
1467 .enable_mask = BIT(0),
1481 .halt_reg = 0x04010,
1483 .enable_reg = 0x04010,
1484 .enable_mask = BIT(0),
1498 .halt_reg = 0x0400c,
1500 .enable_reg = 0x0400c,
1501 .enable_mask = BIT(0),
1515 .halt_reg = 0x0203c,
1517 .enable_reg = 0x0203c,
1518 .enable_mask = BIT(0),
1532 .halt_reg = 0x0302c,
1534 .enable_reg = 0x0302c,
1535 .enable_mask = BIT(0),
1549 .halt_reg = 0x1c004,
1551 .enable_reg = 0x1c004,
1552 .enable_mask = BIT(0),
1561 .halt_reg = 0x56308,
1563 .enable_reg = 0x56308,
1564 .enable_mask = BIT(0),
1578 .halt_reg = 0x5630c,
1580 .enable_reg = 0x5630c,
1581 .enable_mask = BIT(0),
1595 .halt_reg = 0x16024,
1598 .enable_reg = 0x0b004,
1599 .enable_mask = BIT(0),
1613 .halt_reg = 0x16020,
1616 .enable_reg = 0x0b004,
1631 .halt_reg = 0x1601c,
1634 .enable_reg = 0x0b004,
1649 .halt_reg = 0x77004,
1651 .enable_reg = 0x77004,
1652 .enable_mask = BIT(0),
1666 .halt_reg = 0x56010,
1669 .enable_reg = 0x56010,
1670 .enable_mask = BIT(0),
1684 .halt_reg = 0x56014,
1687 .enable_reg = 0x56014,
1688 .enable_mask = BIT(0),
1702 .halt_reg = 0x68304,
1704 .enable_reg = 0x68304,
1705 .enable_mask = BIT(0),
1719 .halt_reg = 0x68300,
1721 .enable_reg = 0x68300,
1722 .enable_mask = BIT(0),
1736 .halt_reg = 0x68240,
1738 .enable_reg = 0x68240,
1739 .enable_mask = BIT(0),
1753 .halt_reg = 0x68190,
1757 .enable_reg = 0x683190,
1758 .enable_mask = BIT(0),
1772 .halt_reg = 0x68244,
1774 .enable_reg = 0x68244,
1775 .enable_mask = BIT(0),
1789 .halt_reg = 0x68324,
1791 .enable_reg = 0x68324,
1792 .enable_mask = BIT(0),
1806 .halt_reg = 0x68320,
1808 .enable_reg = 0x68320,
1809 .enable_mask = BIT(0),
1823 .halt_reg = 0x68248,
1825 .enable_reg = 0x68248,
1826 .enable_mask = BIT(0),
1840 .halt_reg = 0x68310,
1842 .enable_reg = 0x68310,
1843 .enable_mask = BIT(0),
1857 .halt_reg = 0x6824c,
1859 .enable_reg = 0x6824c,
1860 .enable_mask = BIT(0),
1874 .halt_reg = 0x08000,
1876 .enable_reg = 0x08000,
1877 .enable_mask = BIT(0),
1891 .halt_reg = 0x09000,
1893 .enable_reg = 0x09000,
1894 .enable_mask = BIT(0),
1908 .halt_reg = 0x0a000,
1910 .enable_reg = 0x0a000,
1911 .enable_mask = BIT(0),
1925 .halt_reg = 0x2e048,
1928 .enable_reg = 0x2e048,
1929 .enable_mask = BIT(0),
1943 .halt_reg = 0x2e04c,
1945 .enable_reg = 0x2e04c,
1946 .enable_mask = BIT(0),
1960 .halt_reg = 0x58004,
1962 .enable_reg = 0x58004,
1963 .enable_mask = BIT(0),
1977 .halt_reg = 0x58014,
1979 .enable_reg = 0x58014,
1980 .enable_mask = BIT(0),
1994 .halt_reg = 0x75010,
1996 .enable_reg = 0x75010,
1997 .enable_mask = BIT(0),
2011 .halt_reg = 0x75014,
2013 .enable_reg = 0x75014,
2014 .enable_mask = BIT(0),
2028 .halt_reg = 0x75008,
2030 .enable_reg = 0x75008,
2031 .enable_mask = BIT(0),
2045 .halt_reg = 0x75048,
2047 .enable_reg = 0x75048,
2048 .enable_mask = BIT(0),
2062 .halt_reg = 0x7500c,
2064 .enable_reg = 0x7500c,
2065 .enable_mask = BIT(0),
2079 .halt_reg = 0x75018,
2083 .enable_reg = 0x75018,
2084 .enable_mask = BIT(0),
2098 .halt_reg = 0x76010,
2100 .enable_reg = 0x76010,
2101 .enable_mask = BIT(0),
2115 .halt_reg = 0x76014,
2117 .enable_reg = 0x76014,
2118 .enable_mask = BIT(0),
2132 .halt_reg = 0x76008,
2134 .enable_reg = 0x76008,
2135 .enable_mask = BIT(0),
2149 .halt_reg = 0x76048,
2151 .enable_reg = 0x76048,
2152 .enable_mask = BIT(0),
2166 .halt_reg = 0x7600c,
2168 .enable_reg = 0x7600c,
2169 .enable_mask = BIT(0),
2187 .enable_reg = 0x76018,
2188 .enable_mask = BIT(0),
2202 .halt_reg = 0x13004,
2205 .enable_reg = 0x0b004,
2220 .halt_reg = 0x59138,
2222 .enable_reg = 0x59138,
2223 .enable_mask = BIT(0),
2237 .halt_reg = 0x5914c,
2239 .enable_reg = 0x5914c,
2240 .enable_mask = BIT(0),
2254 .halt_reg = 0x5913c,
2256 .enable_reg = 0x5913c,
2257 .enable_mask = BIT(0),
2271 .halt_reg = 0x59150,
2273 .enable_reg = 0x59150,
2274 .enable_mask = BIT(0),
2288 .halt_reg = 0x59154,
2290 .enable_reg = 0x59154,
2291 .enable_mask = BIT(0),
2305 .halt_reg = 0x59148,
2307 .enable_reg = 0x59148,
2308 .enable_mask = BIT(0),
2322 .halt_reg = 0x59144,
2324 .enable_reg = 0x59144,
2325 .enable_mask = BIT(0),
2339 .halt_reg = 0x59140,
2341 .enable_reg = 0x59140,
2342 .enable_mask = BIT(0),
2356 .halt_reg = 0x59128,
2358 .enable_reg = 0x59128,
2359 .enable_mask = BIT(0),
2373 .halt_reg = 0x29024,
2375 .enable_reg = 0x29024,
2376 .enable_mask = BIT(0),
2390 .halt_reg = 0x29084,
2392 .enable_reg = 0x29084,
2393 .enable_mask = BIT(0),
2407 .halt_reg = 0x29008,
2409 .enable_reg = 0x29008,
2410 .enable_mask = BIT(0),
2424 .halt_reg = 0x29004,
2426 .enable_reg = 0x29004,
2427 .enable_mask = BIT(0),
2441 .halt_reg = 0x29028,
2443 .enable_reg = 0x29028,
2444 .enable_mask = BIT(0),
2458 .halt_reg = 0x29020,
2460 .enable_reg = 0x29020,
2461 .enable_mask = BIT(0),
2475 .halt_reg = 0x29044,
2477 .enable_reg = 0x29044,
2478 .enable_mask = BIT(0),
2492 .halt_reg = 0x29060,
2494 .enable_reg = 0x29060,
2495 .enable_mask = BIT(0),
2509 .halt_reg = 0x2908c,
2511 .enable_reg = 0x2908c,
2512 .enable_mask = BIT(0),
2526 .halt_reg = 0x57024,
2528 .enable_reg = 0x57024,
2529 .enable_mask = BIT(0),
2543 .halt_reg = 0x57020,
2545 .enable_reg = 0x57020,
2546 .enable_mask = BIT(0),
2560 .halt_reg = 0x5701c,
2562 .enable_reg = 0x5701c,
2563 .enable_mask = BIT(0),
2577 .halt_reg = 0x4201c,
2579 .enable_reg = 0x4201c,
2580 .enable_mask = BIT(0),
2594 .halt_reg = 0x42018,
2596 .enable_reg = 0x42018,
2597 .enable_mask = BIT(0),
2611 .halt_reg = 0x260a0,
2613 .enable_reg = 0x260a0,
2614 .enable_mask = BIT(0),
2628 .halt_reg = 0x26084,
2630 .enable_reg = 0x26084,
2631 .enable_mask = BIT(0),
2645 .halt_reg = 0x260a4,
2647 .enable_reg = 0x260a4,
2648 .enable_mask = BIT(0),
2662 .halt_reg = 0x26088,
2664 .enable_reg = 0x26088,
2665 .enable_mask = BIT(0),
2679 .halt_reg = 0x26074,
2681 .enable_reg = 0x26074,
2682 .enable_mask = BIT(0),
2696 .halt_reg = 0x26078,
2698 .enable_reg = 0x26078,
2699 .enable_mask = BIT(0),
2713 .halt_reg = 0x26094,
2715 .enable_reg = 0x26094,
2716 .enable_mask = BIT(0),
2730 .halt_reg = 0x26048,
2732 .enable_reg = 0x26048,
2733 .enable_mask = BIT(0),
2747 .halt_reg = 0x2604c,
2749 .enable_reg = 0x2604c,
2750 .enable_mask = BIT(0),
2764 .halt_reg = 0x26024,
2766 .enable_reg = 0x26024,
2767 .enable_mask = BIT(0),
2781 .halt_reg = 0x26040,
2783 .enable_reg = 0x26040,
2784 .enable_mask = BIT(0),
2798 .halt_reg = 0x26034,
2800 .enable_reg = 0x26034,
2801 .enable_mask = BIT(0),
2815 .halt_reg = 0x68200,
2818 .enable_reg = 0x68200,
2819 .enable_mask = BIT(0),
2833 .halt_reg = 0x68160,
2836 .enable_reg = 0x68160,
2837 .enable_mask = BIT(0),
2851 .halt_reg = 0x68214,
2854 .enable_reg = 0x68214,
2855 .enable_mask = BIT(0),
2869 .halt_reg = 0x68210,
2872 .enable_reg = 0x68210,
2873 .enable_mask = BIT(0),
2887 .halt_reg = 0x68204,
2890 .enable_reg = 0x68204,
2891 .enable_mask = BIT(0),
2905 .halt_reg = 0x68208,
2908 .enable_reg = 0x68208,
2909 .enable_mask = BIT(0),
2923 .halt_reg = 0x56108,
2925 .enable_reg = 0x56108,
2926 .enable_mask = BIT(0),
2940 .halt_reg = 0x56110,
2942 .enable_reg = 0x56110,
2943 .enable_mask = BIT(0),
2957 .halt_reg = 0x56114,
2959 .enable_reg = 0x56114,
2960 .enable_mask = BIT(0),
2974 .halt_reg = 0x5610c,
2976 .enable_reg = 0x5610c,
2977 .enable_mask = BIT(0),
2991 .halt_reg = 0x3e044,
2993 .enable_reg = 0x3e044,
2994 .enable_mask = BIT(0),
3008 .halt_reg = 0x3e04c,
3011 .enable_reg = 0x3e04c,
3012 .enable_mask = BIT(0),
3026 .halt_reg = 0x3e050,
3028 .enable_reg = 0x3e050,
3029 .enable_mask = BIT(0),
3043 .halt_reg = 0x3e000,
3045 .enable_reg = 0x3e000,
3046 .enable_mask = BIT(0),
3060 .halt_reg = 0x3e008,
3062 .enable_reg = 0x3e008,
3063 .enable_mask = BIT(0),
3077 .halt_reg = 0x3e080,
3079 .enable_reg = 0x3e080,
3080 .enable_mask = BIT(0),
3094 .halt_reg = 0x3e004,
3096 .enable_reg = 0x3e004,
3097 .enable_mask = BIT(0),
3111 .halt_reg = 0x3e040,
3114 .enable_reg = 0x3e040,
3115 .enable_mask = BIT(0),
3129 .halt_reg = 0x59064,
3131 .enable_reg = 0x59064,
3132 .enable_mask = BIT(0),
3146 .halt_reg = 0x59034,
3148 .enable_reg = 0x59034,
3149 .enable_mask = BIT(0),
3163 .halt_reg = 0x5903c,
3165 .enable_reg = 0x5903c,
3166 .enable_mask = BIT(0),
3180 .halt_reg = 0x59068,
3182 .enable_reg = 0x59068,
3183 .enable_mask = BIT(0),
3197 .halt_reg = 0x59050,
3199 .enable_reg = 0x59050,
3200 .enable_mask = BIT(0),
3214 .halt_reg = 0x59040,
3216 .enable_reg = 0x59040,
3217 .enable_mask = BIT(0),
3231 .halt_reg = 0x59054,
3233 .enable_reg = 0x59054,
3234 .enable_mask = BIT(0),
3248 .halt_reg = 0x59044,
3250 .enable_reg = 0x59044,
3251 .enable_mask = BIT(0),
3265 .halt_reg = 0x59060,
3267 .enable_reg = 0x59060,
3268 .enable_mask = BIT(0),
3282 .halt_reg = 0x5905c,
3284 .enable_reg = 0x5905c,
3285 .enable_mask = BIT(0),
3299 .halt_reg = 0x59058,
3301 .enable_reg = 0x59058,
3302 .enable_mask = BIT(0),
3316 .halt_reg = 0x59048,
3318 .enable_reg = 0x59048,
3319 .enable_mask = BIT(0),
3333 .halt_reg = 0x59038,
3335 .enable_reg = 0x59038,
3336 .enable_mask = BIT(0),
3359 .l = 0x29,
3360 .alpha = 0xaaaaaaaa,
3361 .alpha_hi = 0xaa,
3362 .config_ctl_val = 0x4001075b,
3363 .main_output_mask = BIT(0),
3366 .vco_val = 0x1,
3368 .test_ctl_val = 0x0,
3369 .test_ctl_hi_val = 0x0,
3549 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
3550 [GCC_BLSP1_BCR] = { 0x01000, 0 },
3551 [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
3552 [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
3553 [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
3554 [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
3555 [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
3556 [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
3557 [GCC_BTSS_BCR] = { 0x1c000, 0 },
3558 [GCC_CMN_BLK_BCR] = { 0x56300, 0 },
3559 [GCC_CMN_LDO_BCR] = { 0x33000, 0 },
3560 [GCC_CE_BCR] = { 0x33014, 0 },
3561 [GCC_CRYPTO_BCR] = { 0x16000, 0 },
3562 [GCC_DCC_BCR] = { 0x77000, 0 },
3563 [GCC_DCD_BCR] = { 0x2a000, 0 },
3564 [GCC_DDRSS_BCR] = { 0x1e000, 0 },
3565 [GCC_EDPD_BCR] = { 0x3a000, 0 },
3566 [GCC_GEPHY_BCR] = { 0x56000, 0 },
3567 [GCC_GEPHY_MDC_SW_ARES] = { 0x56004, 0 },
3568 [GCC_GEPHY_DSP_HW_ARES] = { 0x56004, 1 },
3569 [GCC_GEPHY_RX_ARES] = { 0x56004, 2 },
3570 [GCC_GEPHY_TX_ARES] = { 0x56004, 3 },
3571 [GCC_GMAC0_BCR] = { 0x19000, 0 },
3572 [GCC_GMAC0_CFG_ARES] = { 0x68428, 0 },
3573 [GCC_GMAC0_SYS_ARES] = { 0x68428, 1 },
3574 [GCC_GMAC1_BCR] = { 0x19100, 0 },
3575 [GCC_GMAC1_CFG_ARES] = { 0x68438, 0 },
3576 [GCC_GMAC1_SYS_ARES] = { 0x68438, 1 },
3577 [GCC_IMEM_BCR] = { 0x0e000, 0 },
3578 [GCC_LPASS_BCR] = { 0x2e000, 0 },
3579 [GCC_MDIO0_BCR] = { 0x58000, 0 },
3580 [GCC_MDIO1_BCR] = { 0x58010, 0 },
3581 [GCC_MPM_BCR] = { 0x2c000, 0 },
3582 [GCC_PCIE0_BCR] = { 0x75004, 0 },
3583 [GCC_PCIE0_LINK_DOWN_BCR] = { 0x750a8, 0 },
3584 [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
3585 [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
3586 [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
3587 [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
3588 [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
3589 [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
3590 [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
3591 [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
3592 [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
3593 [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
3594 [GCC_PCIE1_BCR] = { 0x76004, 0 },
3595 [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
3596 [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
3597 [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
3598 [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
3599 [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
3600 [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
3601 [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
3602 [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
3603 [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
3604 [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
3605 [GCC_PCIE1_AXI_SLAVE_STICKY_ARES] = { 0x76040, 7 },
3606 [GCC_PCNOC_BCR] = { 0x27018, 0 },
3607 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
3608 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
3609 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
3610 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
3611 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
3612 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
3613 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
3614 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
3615 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
3616 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
3617 [GCC_PCNOC_BUS_TIMEOUT10_BCR] = { 0x48050, 0 },
3618 [GCC_PCNOC_BUS_TIMEOUT11_BCR] = { 0x48058, 0 },
3619 [GCC_PRNG_BCR] = { 0x13000, 0 },
3620 [GCC_Q6SS_DBG_ARES] = { 0x59110, 0 },
3621 [GCC_Q6_AHB_S_ARES] = { 0x59110, 1 },
3622 [GCC_Q6_AHB_ARES] = { 0x59110, 2 },
3623 [GCC_Q6_AXIM2_ARES] = { 0x59110, 3 },
3624 [GCC_Q6_AXIM_ARES] = { 0x59110, 4 },
3625 [GCC_Q6_AXIS_ARES] = { 0x59158, 0 },
3626 [GCC_QDSS_BCR] = { 0x29000, 0 },
3627 [GCC_QPIC_BCR] = { 0x57018, 0 },
3628 [GCC_QUSB2_0_PHY_BCR] = { 0x41030, 0 },
3629 [GCC_SDCC1_BCR] = { 0x42000, 0 },
3630 [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
3631 [GCC_SPDM_BCR] = { 0x2f000, 0 },
3632 [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
3633 [GCC_TCSR_BCR] = { 0x28000, 0 },
3634 [GCC_TLMM_BCR] = { 0x34000, 0 },
3635 [GCC_UBI0_AXI_ARES] = { 0x680},
3636 [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
3637 [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
3638 [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
3639 [GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
3640 [GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
3641 [GCC_UBI32_BCR] = { 0x19064, 0 },
3642 [GCC_UNIPHY_BCR] = { 0x56100, 0 },
3643 [GCC_UNIPHY_AHB_ARES] = { 0x56104, 0 },
3644 [GCC_UNIPHY_SYS_ARES] = { 0x56104, 1 },
3645 [GCC_UNIPHY_RX_ARES] = { 0x56104, 4 },
3646 [GCC_UNIPHY_TX_ARES] = { 0x56104, 5 },
3647 [GCC_UNIPHY_SOFT_RESET] = {0x56104, 0 },
3648 [GCC_USB0_BCR] = { 0x3e070, 0 },
3649 [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
3650 [GCC_WCSS_BCR] = { 0x18000, 0 },
3651 [GCC_WCSS_DBG_ARES] = { 0x59008, 0 },
3652 [GCC_WCSS_ECAHB_ARES] = { 0x59008, 1 },
3653 [GCC_WCSS_ACMT_ARES] = { 0x59008, 2 },
3654 [GCC_WCSS_DBG_BDG_ARES] = { 0x59008, 3 },
3655 [GCC_WCSS_AHB_S_ARES] = { 0x59008, 4 },
3656 [GCC_WCSS_AXI_M_ARES] = { 0x59008, 5 },
3657 [GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 },
3658 [GCC_WCSS_Q6_BCR] = { 0x18004, 0 },
3659 [GCC_WCSSAON_RESET] = { 0x59010, 0},
3660 [GCC_GEPHY_MISC_ARES] = { 0x56004, 0 },
3673 .max_register = 0x7fffc,