clk/qcom/clk-alpha-pll.h

1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/clk-provider.h>
12 #include "clk-regmap.h"
65 #define VCO(a, b, c) { \  macro
72  * struct clk_alpha_pll - phase locked loop (PLL)
73  * @offset: base address of registers
74  * @vco_table: array of VCO settings
79 	u32 offset;  member
94  * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
95  * @offset: base address of registers
97  * @width: width of post-divider
98  * @post_div_shift: shift to differentiate between odd & even post-divider
99  * @post_div_table: table with PLL odd and even post-divider settings
100  * @num_post_div: Number of PLL post-divider settings
105 	u32 offset;  member